Ferroelectric memory device and its driving method

1. A ferroelectric memory device comprising:

a plurality of memory cells; and

a control section that stores memory data indicated by a data signal when a write control signal changes from a first logical value to a second logical value, wherein:

when the write control signal indicates the first logical value, the control section writes preliminary data in a first memory cell, and

when the write control signal changes from the first logical value to the second logical value, the control section retains the preliminary data in the first memory cell, or writes the memory data in the first memory cell to store the memory data in the first memory cell.

2. A ferroelectric memory device according to claim 1 , further comprising a plate line and a first bit line connected to the first memory cell,

wherein the first memory cell has a first ferroelectric capacitor having one end connected to the first bit line through a transistor and another end connected to the plate line, and

the control section includes:

a plate line control circuit that controls a potential on the plate line such that the potential on the plate line becomes higher than a potential on the first bit line to thereby write the preliminary data in the first ferroelectric capacitor, and

a bit line control circuit that controls the potential on the first bit line such that the potential on the first bit line becomes higher than the potential on the plate line to thereby write the memory data in the first ferroelectric capacitor.

3. A ferroelectric memory device according to claim 1 , further comprising a second memory cell, wherein:

when the preliminary data is to be written in the first memory cell, the control section reads memory data stored in the second memory cell, and

when the write control signal changes from the first logical value to the second logical value, the control section writes in the second memory cell the memory data read out from the second memory cell to re-store the memory data.

4. A ferroelectric memory device according to claim 2 , wherein the plate line control circuit and the bit line control circuit control the potentials on the plate line and the first bit line, respectively, such that the one end and the other end of the first ferroelectric capacitor have a generally identical potential, after the preliminary data is written in the first ferroelectric capacitor.

5. A ferroelectric memory device according to claim 2 , further comprising a data pin that receives the data signal from outside of the ferroelectric memory device, and a transfer circuit that switches as to whether the data signal received by the data pin is to be transferred to the bit line control circuit, wherein:

the bit line control circuit includes a first write circuit that retains the data signal, and a first switch provided between the first bit line and the first write circuit,

the transfer circuit transfers the data signal to the first write circuit when the write control signal indicates the first logical value,

the first switch connects the first write circuit and the first bit line when the write control signal changes from the first logical value to the second logical value, and

the first write circuit, when the first write circuit is connected to the first bit line, controls the potential on the first bit line based on the data signal transferred to thereby store the memory data in the first memory cell.

6. A ferroelectric memory device according to claim 5 , further comprising a main bit line connected to a plurality of sub-bit lines including the first bit line, wherein:

the first switch is provided between the main bit line and the first bit line, and

the first write circuit is connected to the first bit line through the main bit line and the first switch.

7. A ferroelectric memory device according to claim 5 , wherein:

the bit line control circuit further includes a grounding circuit that switches as to whether the first bit line is to be grounded,

the first switch cuts off the first bit line from the first write circuit when the transfer circuit is transferring the data signal to the first write circuit, and

the grounding circuit and the plate line control circuit put the potentials on the first bit line and the plate line to a ground potential when the transfer circuit is transferring the data signal to the write circuit.

8. A ferroelectric memory device according to claim 5 , wherein:

the bit line control circuit further includes a grounding circuit connected to the first bit line, which switches as to whether the first bit line is to be grounded,

when the first switch cuts off the first bit line from the first write circuit, the grounding circuit grounds the first bit line to thereby write the preliminary data in the first ferroelectric capacitor, and the transfer circuit starts transferring the data signal to the write circuit.

9. A ferroelectric memory device according to claim 3 , wherein, when the write signal indicates the first logical value, the control section reads memory data stored in the first memory cell and the second memory cell, and writes the preliminary data in the first memory cell and the second memory cell from which the memory data are read out.

10. A ferroelectric memory device according to claim 3 , further comprising:

a first bit line and a second bit line connected to the first memory cell and the second memory cell, respectively,

a plate line connected to the first memory cell and the second memory cell,

a data pin that receives the data signal from outside of the ferroelectric memory device, and

a transfer circuit that switches as to whether the data signal received by the data pin is to be transferred to the control section, wherein:

the control section includes:

a plate line control circuit that controls a potential on the plate line,

a first sense amplifier that controls a potential on the first bit line based on the data signal, or retains memory data stored in the first memory cell based on the potential on the first bit line,

a second sense amplifier that controls a potential on the second bit line based on the data signal, or retains memory data stored in the second memory cell based on the potential on the second bit line,

a first switch and a second switch that switch as to whether the first bit line and the second bit line are to be connected to the first sense amplifier and the second sense amplifier, respectively,

a first grounding circuit and a second grounding circuit that switch as to whether the first bit line and the second bit line are to be grounded, respectively, and

a selection circuit that supplies the data signal transferred by the transfer circuit to one of the first sense amplifier and the second sense amplifier, wherein:

the plate line control circuit, the first grounding circuit and the second grounding circuit place the first bit line and the second bit line in a floating state, and readout memory data stored in the first memory cell and the second memory cell,

the first sense amplifier and the second sense amplifier retain the memory data read out from the first memory cell and the second memory cell, respectively,

the first switch and the second switch cut off the first bit line and the second bit line from the first sense amplifier and the second sense amplifier, respectively, when the first sense amplifier and the second sense amplifier retain the memory data read out,

the plate line control circuit, the first grounding circuit and the second grounding circuit write the preliminary data at least in the first bit line, when the first bit line and the second bit line are cut off from the first sense amplifier and the second sense amplifier, respectively,

the selection circuit transfers the data signal transferred by the transfer circuit to the first sense amplifier, when the first bit line and the second bit line are cut off from the first sense amplifier and the second sense amplifier, respectively, and

when the write control signal changes from the first logical value to the second logical value, the first sense amplifier writes the memory data indicated by the data signal transferred in the first memory cell, and the second sense amplifier re-writes the memory data readout in the second memory cell.

11. A driving method for driving a ferroelectric memory device that stores memory data indicated by a data signal in a memory cell when a write control signal changes from a first logical value to a second logical value, the driving method comprising:

a step of writing preliminary data in a first memory cell when the write control signal indicates the first logical value; and

a step of retaining the preliminary data in the first memory cell, or writing the memory data in the first memory cell to thereby store the memory data in the first memory cell, when the write control signal changes from the first logical value to the second logical value.