Maintaining synchronization of multiple data channels with a common clock signal
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘x’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.
1. A method of transferring a plurality of sequences of parallel data elements, said method comprising:
receiving each of said plurality of sequences of parallel data elements on a corresponding one of a plurality of parallel data channels;
converting each of said plurality of sequences of parallel data elements to a corresponding one of a plurality of sequences of serial data elements;
sending each of said plurality of sequences of serial data elements on a corresponding one of a plurality of serial data channels, wherein said sending uses a second common clock signal associated with said plurality of serial data channels, wherein said plurality of serial data channels are synchronized with said second common clock signal;
generating a sequence of synchronization signals with a short interval between successive ones of said sequence of synchronization signals; and
ensuring that said plurality of parallel data channels are synchronized to a common time reference in response to each of said sequence of synchronization signals such that a first common clock signal is used to receive all of said plurality of sequences of parallel data elements on said plurality of parallel data channels, wherein the first common clock signal and the second common clock signal are periodic.
2. The method of claim 1 , wherein each of said parallel data elements comprises N bits, wherein N represents an integer, wherein said short interval equals M×N of a clock period of said second common clock signal, wherein M also represents an integer and ‘x’ represents a multiplication operation.
3. The method of claim 2 , wherein each of said parallel data elements comprises a byte containing 8 bits, and M equals 1, such that said sequence of synchronization signals are generated periodically with a period of eight times the period of said second common clock signal.
4. The method of claim 3 , wherein each of said synchronization signals comprises a pulse.
5. The method of claim 1 , further comprising sending said second common clock signal in parallel with said plurality of serial data channels.
6. The method of claim 1 , further comprising:
sending said first common clock signal to a block sending said plurality of sequences of parallel data elements,
wherein a parallel data element is received from each of said plurality of parallel data channels in a cycle of said first common clock signal.
7. The method of claim 1 , wherein said ensuring comprises adjusting a timing of said first common clock signal according to said sequence of synchronization signals.
8. The method of claim 1 , wherein said each of said sequence of synchronization signals is generated using said second common clock signal.
9. The method of claim 1 , wherein the first common clock signal and second common clock signal are generated by a phase lock loop (PLL).
10. A method of transferring a plurality of sequences of serial data elements, said method comprising:
receiving each of said plurality of sequences of serial data elements on a corresponding one of a plurality of serial data channels, wherein said receiving uses a second common clock signal associated with said plurality of serial data channels, wherein said plurality of serial data channels are synchronized with said second common clock signal;
converting each of said plurality of sequences of serial data elements to a corresponding one of a plurality of sequences of parallel data elements;
sending each of said plurality of sequences of parallel data elements on a corresponding one of a plurality of parallel data channels;
generating a sequence of synchronization signals with a short interval between successive ones of said sequence of synchronization signals; and
ensuring that said plurality of parallel data channels are synchronized to a common time reference in response to each of said sequence of synchronization signals such that all of said sequences of parallel data elements are sent on said plurality of parallel data channels using a first common clock signal, wherein the first common clock signal and the second common clock signal are periodic.
11. The method of claim 10 , wherein each of said parallel data elements comprises N bits, wherein N represents an integer, wherein said short interval equals M×N of a clock period of said second common clock signal, wherein M also represents an integer and ‘x’ represents a multiplication operation.
12. The method of claim 11 , wherein each of said parallel data elements comprises a byte containing 8 bits, and M equals 1, such that said sequence of synchronization signals are generated periodically with a period of eight times the period of said second common clock signal.
13. The method of claim 12 , wherein each of said sequence of synchronization signals comprises a pulse.
14. The method of claim 10 , further comprising receiving said second common clock signal in parallel with said plurality of serial data channels.
15. The method of claim 10 , further comprising:
sending said first common clock signal to a block receiving said plurality of sequences of parallel data elements,
wherein a parallel data element is sent on each of said plurality of parallel data channels in a cycle of said first common clock signal.
16. The method of claim 10 , wherein said ensuring comprises adjusting a timing of said first common clock signal according to said sequence of synchronization signals.
17. The method of claim 10 , wherein said each of said sequence of synchronization signals is generated using said second common clock signal.
18. The method of claim 10 , wherein the first common clock signal and second common clock signal are generated by a phase lock loop (PLL).
19. A line card provided between a switch fabric and a network, said line card transferring a plurality of sequences of parallel data elements, said line card comprising:
means for receiving each of said plurality of sequences of parallel data elements on a corresponding one of a plurality of parallel data channels;
means for converting each of said plurality of sequences of parallel data elements to a corresponding one of a plurality of sequences of serial data elements;
means for sending each of said plurality of sequences of serial data elements on a corresponding one of a plurality of serial data channels, wherein said means for sending sends a second common clock signal associated with said plurality of serial data channels, wherein said plurality of serial data channels are synchronized with said second common clock signal;
means for generating a sequence of synchronization signals with a short interval between successive ones of said sequence of synchronization signals; and
means for ensuring that said plurality of parallel data channels are synchronized to a common time reference in response to each of said sequence of synchronization signals such that a first common clock signal is used to receive all of said plurality of sequences of parallel data elements on said plurality of parallel data channels, wherein the first common clock signal and the second common clock signal are periodic.
20. The line card of claim 19 , wherein each of said parallel data elements comprises a byte containing 8 bits, such that said sequence of synchronization signals are generated periodically with a period of eight times the period of said second common clock signal and wherein each of said sequence of synchronization signals comprises a pulse.
21. The line card of claim 19 , further comprising:
a core logic; and
means for sending said first common clock signal to said core logic, wherein said core logic sends a parallel data element for each of said plurality of parallel data channels in a cycle of said first common clock signal.
22. The line card of claim 21 , wherein said means for ensuring adjusts a timing of said first common clock signal according to said sequence of synchronization signals.
23. The method of claim 19 , wherein the first common clock signal and second common clock signal are generated by a phase lock loop (PLL).
24. A line card provided between a switch fabric and a network, said line card transferring a plurality of sequences of serial data elements, said line card comprising:
means for receiving each of said plurality of sequences of serial data elements on a corresponding one of a plurality of serial data channels;
means for converting each of said plurality of sequences of serial data elements to a corresponding one of a plurality of sequences of parallel data elements;
means for sending each of said plurality of sequences of parallel data elements on a corresponding one of a plurality of parallel data channels using a first common clock signal;
means for generating a sequence of synchronization signals with a short interval between successive ones of said sequence of synchronization signals;
means for ensuring that said plurality of parallel data channels are synchronized with said first common clock signal in response to each of said sequence of synchronization signals; and
means for receiving a second common clock signal in parallel with said plurality of serial data channels, wherein said means for receiving uses said second common clock signal associated with said plurality of serial data channels, wherein said plurality of serial data channels are synchronized with said second common clock signal, wherein the first common clock signal and the second common clock signal are periodic.
25. The line of claim 24 , further comprising:
a core logic block; and
means for sending said first common clock signal to said core logic block receiving said plurality of sequences of parallel data elements,
wherein a parallel data element is sent on each of said plurality of parallel data channels in a cycle of said first common clock signal.
26. The method of claim 25 , wherein said means for ensuring adjusts a timing of said first common clock signal according to said sequence of synchronization signals.
27. The method of claim 26 , wherein said each of said sequence of synchronization signals is generated using said second common clock signal.
28. The method of claim 24 , wherein the first common clock signal and second common clock signal are generated by a phase lock loop (PLL).