Semiconductor passivation deposition process for interfacial adhesion
A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas including at least one common chemical element.
1. An integrated circuit (IC) comprising:
a substrate comprising at least one level of interconnection;
an insulating layer formed directly on a surface of the substrate;
at least one bond pad formed directly on the insulating layer, the at least one bond pad coupled through the insulating layer to the at least one level of interconnection of the substrate;
an adhesion layer formed on a surface of the insulating layer such that the insulating layer is disposed between the adhesion layer and the substrate; and
a passivation layer formed on a surface of said adhesion layer and a portion of a top surface of the bond pad that is less than the entire top surface.
2. The integrated circuit of claim 1 , wherein the passivation layer is a first passivation layer, the integrated circuit further comprising a second passivation layer formed upon said first passivation layer.
3. The integrated circuit of claim 1 , wherein said insulating layer comprises an oxide layer comprising silicon dioxide (SiO 2 ).
4. The integrated circuit of claim 1 , wherein said adhesion layer includes silicon oxynitride.
5. The integrated circuit of claim 1 , wherein said passivation layer includes silicon nitride (Si 3 N 4 ).
6. The integrated circuit of claim 2 , wherein said second passivation layer includes polyimide.
7. An integrated circuit comprising:
a substrate;
an insulating layer formed directly on a surface the substrate;
at least one bond pad formed directly on the insulating layer;
a composite film comprising:
a first layer, and
a second layer of a material different than a material of the first layer, wherein the first layer is an adhension layer and disposed between the insulating layer and the second layer,
wherein the first layer and the second layer comprise one common chemical element other than silicon, and
wherein the second layer is a passivation layer formed on the first layer and a portion of a top surface of the bond pad that is less than the entire top surface.
8. The integrated circuit of claim 7 , wherein said first layer includes silicon oxynitride.
9. The integrated circuit of claim 8 , wherein said second layer includes silicon nitride (Si 3 N 4 ).
10. The integrated circuit of claim 1 , wherein the insulating layer includes a micro roughened surface.