IP Library Granted Patent US 7,208,348
Granted Patent B2
US 7,208,348 · App. 10/994,995 · Granted Apr 24, 2007

Methods of fabricating a via-in-pad with off-center geometry

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,208,348
App. No.
10/994,995
Granted
Apr 24, 2007
Kind
B2
Abstract

The electrical contacts, such as ball grid array (BGA) solder balls, of an integrated circuit (IC) are coupled to printed circuit board (PCB) bonding pads that include vias. According to an embodiment of an electronic assembly, the vias are formed off-center, so as to inhibit bridging between adjacent solder balls during a solder reflow operation by minimizing the effect of solder ball ballooning resulting from outgassing of a thermally expansive substance, such as a volatile organic compound (VOC) from the via channels. The bonding pads are separated into two groups, each having vias offset in a different direction, so that asymmetric surface tension forces in the molten solder during a solder reflow operation do not cause the IC to slide to one side. A substrate, an electronic assembly, an electronic system, and fabrication methods are also described.

Claims (17)

1. A method comprising:

forming on a substrate a plurality of mounting lands and a centerline separating the plurality of lands into two substantially equal portions, each land having a circular perimeter and a geometric center, wherein each land has a via offset therein extending into the substrate, wherein each via has a geometric center located in a region between the geometric center and the perimeter of its associated land, wherein the lands comprise a first group having vias whose geometric centers are offset in a first direction with respect to the geometric centers of the corresponding lands of the first group, wherein the lands comprise a second group having vias whose geometric centers are offset in a second direction with respect to the geometric centers of the corresponding lands of the second group, wherein the first and second groups are on opposite sides of the centerline; and wherein the first direction is different from the second direction.

2. The method recited in claim 1 , wherein in the forming operation the vias are formed by drilling.

3. The method recited in claim 1 , wherein vias of adjacent lands within either the first group or second group are drilled at substantially the same distance from the geometric centers of the respective lands, and wherein the offsets of such vias from the geometric centers of the respective lands have substantially the same angle.

4. The method recited in claim 1 , wherein the first direction is opposite to the second direction.

5. The method recited in claim 1 , wherein the vias are circular.

6. The method recited in claim 1 and further comprising:

aligning an integrated circuit package having contacts comprising electrically conductive material with respect to the lands; and

heating the electrically conductive material and the lands until they join.

7. The method recited in claim 6 , wherein the contacts form a portion of a ball grid array.

8. The method recited in claim 6 , further comprising:

prior to aligning, applying a material over the surface of the substrate, including the vias, the material comprising a thermally expansive substance.

9. The method recited in claim 8 , wherein the material comprises a volatile organic compound.

10. The method recited in claim 8 , wherein the material is from the group comprising a solder mask, a solder flux, a solder paste, a solvent, and a via cap.

11. The method recited in claim 6 , wherein the electrically conductive material comprises solder.

12. The method recited in claim 11 , wherein in the heating operation the solder adheres to the entire respective land without any other material intervening between the solder and the respective land.

13. The method recited in claim 6 , wherein the contacts are solder balls.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 0975161400 · Dec 29, 2000
Related Publication 20050090040A1 · Apr 28, 2005