Enhancement mode single electron transistor

1. A transistor comprising:

a bottom dielectric layer;

a first layer on at least a portion of the bottom dielectric layer and having a first bandgap defining a maximum valance energy level below the first bandgap and above the Fermi energy of the first layer;

a second layer on at least a portion of the first layer and having a second bandgap defining a minimum conduction energy level above the second bandgap;

wherein the second layer comprises a material having a bulk bandgap when the material is in bulk form;

wherein the second layer has a thickness that is less than a maximum thickness, such that the second bandgap is larger than the bulk bandgap, and such that the minimum conduction energy level is within the first bandgap; and

wherein the maximum valance energy level and the Fermi energy are within the second bandgap;

a top dielectric layer on at least a portion of the second layer;

wherein at least one of the bottom dielectric layer and the top dielectric layer is partially p-doped;

wherein the first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer; and

wherein the first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer; and

a gate electrode on a portion of the top dielectric layer over a portion of the hole wire;

wherein the gate electrode divides the top dielectric layer into a source contact and a drain contact;

wherein the gate electrode comprising a metal layer and an oxide layer.

2. The transistor of claim 1 , wherein the first layer comprises Al x Ga 1-x Sb.

3. The transistor of claim 1 ;

wherein the second layer comprises InAs; and

wherein the thickness of the second layer is less than about 10 nm.

4. The transistor of claim 1 , wherein the bottom dielectric layer and the top dielectric layer both comprise Al y Ga 1-y Sb.

5. The transistor of claim 1 , wherein the hole conducting channel is no more than about 100 nm wide.

6. The transistor of claim 1 , wherein a portion of the second layer below the gate electrode and above the hole wire is a quantum dot.

7. The transistor of claim 6 , wherein the dimensions of the quantum dot are no more than about 100 nm×100 nm.

8. The transistor of claim 6 , further comprising:

an isolation gate electrode, whereby a voltage applied to the isolation gate changes the probability of an electron coupling to or tunneling into or out of the adjacent quantum dot.

9. A logic gate comprising:

two of the transistors of claim 1 ; and

a coupling gate between the transistors, whereby a voltage applied to the coupling gate can cause entanglement among one or more electrons in each quantum dot.

10. A quantum computing device comprising a plurality of qubits, at least one qubit comprising the transistor of claim 1 .

11. A method of using the transistor of claim 1 comprising:

increasing a positive bias applied to the gate electrode until the source to drain conductance decreases to zero.

12. The method of claim 11 , further comprising:

further increasing the bias until the conductance increases to a maximum.

13. The method of claim 12 , further comprising:

further increasing the bias until the conductance returns to zero.

14. The method of claim 13 , further comprising:

further increasing the bias to one or more additional conductance maxima.

15. A method of using the transistor of claim 1 comprising:

applying a positive bias to the gate electrode of a magnitude that causes the transistor to exhibit resonant tunneling transistor behavior.

16. A method of making a transistor comprising:

depositing a first layer on at least a portion of a bottom dielectric layer, wherein the first layer has a first bandgap defining a maximum valance energy level below the first bandgap and above the Fermi energy of the first layer;

depositing a second layer on at least a portion of the first layer;

wherein the second layer has a second bandgap defining a minimum conduction energy level above the second bandgap;

wherein the second layer comprises a material having a bulk bandgap when the material is in bulk form;

wherein the second layer has a thickness that is less than a maximum thickness, such that the second bandgap is larger than the bulk bandgap, and such that the minimum conduction energy level is within the first bandgap; and

wherein the maximum valance energy level and the Fermi energy are within the second bandgap;

depositing a top dielectric layer on at least a portion of the second layer;

wherein at least one of the bottom dielectric layer and the top dielectric layer is partially p-doped;

wherein the first layer and the second layer form a quantum well between the bottom dielectric layer and the top dielectric layer; and

wherein the first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer;

depositing a gate electrode on a portion of the top dielectric layer over a portion of the hole wire;

wherein the gate electrode divides the top dielectric layer into a source electrode and a drain electrode.

17. The method of claim 16 ;

wherein the first layer comprises Al x Ga 1-x Sb;

wherein the second layer comprises InAs;

wherein the thickness of the second layer is less than about 10 nm;

wherein the bottom dielectric layer and the top dielectric layer both comprise Al y Ga 1-y Sb; and

wherein the gate electrode comprises a metal layer on an oxide layer.

18. The method of claim 17 , wherein the first layer, the second layer, and the top dielectric layer are configured to form a hole wire by etching of a portion of each of the first layer, the second layer, and the top dielectric layer.

19. The method of claim 18 ;

wherein etching the top dielectric layer and the first layer comprises chemical etching with a solution comprising hydrofluoric acid, hydrogen peroxide, and lactic acid; and

wherein etching the second layer comprises chemical etching with a solution comprising acetic acid, hydrogen peroxide and water.

20. The method of claim 19 , wherein the ratios of the hydrofluoric acid, hydrogen peroxide, and lactic acid in the etchant solution are from about 1:1:100 to about 1:1:200 by volume.

21. The method of claim 16 , wherein each depositing step is performed by a method independently selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, and metal evaporation.