Stacked semiconductor packages
View Patent ↗A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.
1. A semiconductor package structure comprising a plurality of stacked semiconductor packages, each of the semiconductor packages comprising:
a substrate having a front surface and a back surface opposite to the front surface, the front surface being formed with a chip attach area and a plurality of bond fingers around the chip attach area;
at least one chip having an active surface and a non-active surface opposite to the active surface, wherein the chip is mounted via its non-active surface on the chip attach area, and the active surface of the chip is formed with a plurality of electric contacts;
a dielectric layer applied over the front surface of the substrate, for covering the active surface of the chip and the front surface of the substrate, with the electric contacts and the bond fingers being exposed from the dielectric layer;
a conductive trace layer formed on the dielectric layer, for electrically connecting the electric contacts to the bond fingers;
an insulating layer for covering the conductive trace layer and the dielectric layer, with a portion of the conductive trace layer being exposed from the insulating layer; and
a plurality of solder balls implanted on the back surface of the substrate;
wherein the solder balls of an overlying one of the semiconductor packages are electrically connected to the portion of the conductive trace layer exposed from the insulating layer of an underlying one of the semiconductor packages so as to stack the overlying one of the semiconductor packages on the underlying one of the semiconductor packages.
2. The semiconductor package structure of claim 1 , wherein the chip is ground to a thickness below 3 mils.
3. The semiconductor package structure of claim 1 , wherein the dielectric layer is made of an electrically insulating material selected from the group consisting of polyimide and epoxy resin.
4. The semiconductor package structure of claim 1 , wherein the insulating layer is made of epoxy resin or polyimide.