Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
1. A method of forming a dual damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer to provide electrical coupling to a conductive feature in the existing interconnect structure, the method comprising:
forming an etch-stop layer directly on the existing interconnect structure;
forming dielectric layer over the etch-stop layer;
forming a resist pattern over the dielectric layer;
forming a via cavity through a portion of the dielectric layer to expose a portion of the etch-stop layer;
then, extending the via cavity through a portion of the etch-stop layer to expose the conductive feature in the existing interconnect structure with substantially no processing steps between forming and extending the via cavity;
then, removing the resist pattern;
then, etching the dielectric layer to form a trench cavity in the dielectric layer; and
forming a conductive material in the trench and via cavities to provide electrical coupling to the conductive feature in the existing interconnect structure.
2. The method of claim 1 , wherein forming the etch-stop layer comprises depositing a layer of SiN or SiC over the existing interconnect structure and wherein forming the dielectric layer comprises depositing a layer of low-k dielectric material over the etch-stop layer.
3. The method of claim 1 , wherein forming the via cavity through the portion of the dielectric layer comprises etching the portion of the dielectric layer to form the via cavity and to expose the portion of the etch-stop layer using a via etch process, and wherein extending the via cavity through the portion of the etch-stop layer comprises etching an exposed portion of the etch-stop layer to expose the conductive feature in the existing interconnect structure using an etch-stop etch process.
4. The method of claim 3 , wherein the via etch process comprises an RIE etch, and wherein the etch-stop etch process comprises an RIE etch.
5. The method of claim 1 , wherein forming the via cavity and extending the via cavity are performed concurrently.
6. The method of claim 1 , wherein forming the via cavity and extending the via cavity are performed in-situ in a single etch tool.
7. The method of claim 1 , wherein extending the via cavity is performed immediately after forming the via cavity.