Etch stop layer system
View Patent ↗A semiconductor structure including a uniform etch-stop layer. The uniform etch stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 . A method for forming a semiconductor structure includes forming a uniform etch-stop layer providing a handle wafer, and bonding the uniform etch-stop layer to the handle wafer. The uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
1. A semiconductor structure comprising:
a layer structure comprising a uniform etch-stop layer having a doping level below 10 18 atoms/cm 3 and a substantially relaxed graded layer,
wherein the uniform etch-stop layer comprises substantially relaxed Si 1−y and y>0.19.
2. A semiconductor structure comprising:
a layer structure including a uniform etch-stop layer having a doping level below 10 18 atoms/cm 3 ,
wherein the layer structure comprises a substantially relaxed layer disposed under the uniform etch-stop layer and a first strained layer disposed over the uniform etch-stop layer.
3. The semiconductor structure of claim 2 , wherein the first strained layer comprises Si 1−z Ge z and 0≦z<1.
4. A semiconductor structure, comprising
a layer structure including a strained Si 1−z Ge z layer, and
a handle wafer comprising an insulator, the layer structure being bonded to the handle wafer,
wherein 0≦z<1, the layer structure includes a substantially relaxed uniform etch-stop layer disposed over a substantially relaxed layer comprising graded Si 1−x Ge x , the strained Si 1−z Ge z layer is disposed over the uniform etch-stop layer, and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
5. A semiconductor structure comprising:
a layer structure including a strained Si 1−z Ge z layer;
a handle wafer comprising an insulator, the layer structure being bonded to the handle wafer; and
an insulator layer disposed over the layer structure,
wherein 0≦z<1, the layer structure includes a substantially relaxed uniform etch-stop layer disposed over a substantially relaxed layer, the strained Si 1−z Ge z layer is disposed over the uniform etch-stop layer, and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
6. A semiconductor structure comprising:
a layer structure including a strained Si 1−z Ge z layer; and
a handle wafer comprising an insulator, the layer structure being bonded to the handle wafer,
wherein 0≦z<1, the layer structure comprises a substantially relaxed uniform etch-stop layer and substantially relaxed graded layer disposed over the substantially relaxed layer, the strained Si 1−z Ge z layer is disposed over the uniform etch-stop layer, and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
7. The semiconductor structure of claim 6 , wherein the substantially relaxed graded layer comprises Si 1−x Ge x .
8. A semiconductor structure comprising:
a first uniform etch-stop layer;
a second etch-stop layer disposed over the uniform etch-stop layer;
a substantially relaxed layer disposed over the second etch-stop layer;
a substrate disposed over the relaxed layer; and
an insulator layer disposed over the substantially relaxed layer, between the relaxed layer and the substrate,
wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
9. A semiconductor structure comprising:
a first uniform etch-stop layer;
a second etch-stop layer disposed over the uniform etch-stop layer;
a substantially relaxed layer disposed over the second etch-stop layer; and
a substantially relaxed graded layer,
wherein the first uniform etch-stop layer is disposed over the graded layer and the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
10. The semiconductor structure of claim 9 , wherein the substantially relaxed graded layer comprises Si 1−x Ge x .
11. The semiconductor structure of claim 9 , further comprising:
a first substrate,
wherein the substantially relaxed graded layer is disposed on the first substrate.
12. A method for forming a semiconductor structure, the method comprising:
forming a uniform etch-stop layer;
providing a handle wafer; and
bonding the uniform etch-stop layer directly to the handle wafer,
wherein said uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
13. The method of claim 12 , wherein the uniform etch-stop layer comprises substantially relaxed Si 1−y Ge y .
14. The method of claim 12 , further comprising:
planarizing a surface of the uniform etch-stop layer prior to bonding.
15. A method for forming a semiconductor structure, the method comprising:
forming a uniform etch-stop layer;
providing a handle wafer;
bonding the uniform etch-stop layer to the handle wafer; and
forming a substantially relaxed graded layer before forming the uniform etch-stop layer,
wherein the uniform etch-stop layer is formed over the substantially relaxed graded layer and said uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
16. The method of claim 15 , wherein the relaxed graded layer comprises Si 1−x Ge x .
17. The method of claim 15 , further comprising:
releasing the etch-stop layer by removing at least a portion of the graded layer.
18. The method of claim 15 , wherein releasing the etch-stop layer comprises a wet etch.
19. The method of claim 15 , further comprising:
providing a semiconductor substrate,
wherein the substantially relaxed graded layer is formed over the semiconductor substrate.
20. A method for forming a semiconductor substrate, the method comprising:
providing a first substrate;
forming a layer structure over the first substrate by:
forming a uniform etch-stop layer over the first substrate; and
forming a strained layer over the uniform etch-stop layer; and
releasing the strained layer by removing at least a portion of the uniform etch-stop layer,
wherein the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
21. The method of claim 20 , wherein releasing the strained layer comprises a wet etch.
22. A method comprising:
providing a first substrate;
forming a layer structure over the first substrate by:
forming a substantially relaxed graded layer over the first substrate;
forming a uniform etch-stop layer over the graded layer;
forming a strained layer over the uniform etch-stop layer; and
releasing the strained layer by removing at least a portion of the graded layer and at least a portion of the uniform etch-stop layer,
wherein the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
23. The method of claim 22 , wherein releasing the strained layer comprises a wet etch.
24. A method for forming a semiconductor structure, the method comprising:
forming a layer structure by:
forming a uniform etch-stop layer; and
forming a strained Si 1−z Ge z layer over the uniform etch-stop layer, and
bonding the layer structure to a handle wafer comprising an insulator; and
releasing the strained layer by removing at least a portion of the uniform etch-stop layer,
wherein 0≦z<1 and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
25. The method of claim 24 , wherein releasing the strained layer comprises a wet etch.
26. A method for forming a semiconductor structure, the method comprising:
forming a layer structure by:
forming a substantially relaxed graded layer;
forming a uniform etch-stop layer over the substantially graded layer; and
forming a strained Si 1−z Ge z layer over the uniform etch-stop layer, and
bonding the layer structure to a handle wafer comprising an insulator,
wherein 0≦z<1 and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
27. The method of claim 26 , wherein the relaxed graded layer comprises Si 1−x Ge x .
28. The method of claim 26 , further comprising:
releasing the strained layer by removing at least a portion of the graded layer and at least a portion of the uniform etch-stop layer.
29. The method of claim 28 , wherein releasing the strained layer comprises a wet etch.
30. The method of claim 26 , further comprising:
forming an insulator layer over the layer structure.
31. The method of claim 26 , further comprising:
providing a substrate,
wherein the layer structure is formed over the substrate.
32. The method of claim 31 , further comprising:
releasing the strained layer by removing at least a portion of the substrate, at least a portion of the graded layer, and at least a portion of the uniform etch-stop layer.
33. The method of claim 32 , wherein releasing the strained layer comprises a wet etch.
34. A method for forming a semiconductor structure, the method comprising:
forming a strained etch-stop layer; and
forming a substantially relaxed Si 1−w Ge w layer directly over and in contact with the etch-stop layer,
wherein w>0, the etch-stop layer comprises Si 1−z , Ge z , and z=0.
35. A method for forming a semiconductor structure, the method comprising:
forming a first uniform etch-stop layer;
forming a second etch-stop layer over the uniform etch-stop layer; and
forming a substantially relaxed layer over the second etch-stop layer,
wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 , the second etch-stop layer comprises strained Si 1−z Ge z , and z=0.
36. A method for forming a semiconductor structure, the method comprising:
forming a first uniform etch-stop layer;
forming a second etch-stop layer over the uniform etch-stop layer;
forming a substantially relaxed layer over the second etch-stop layer;
bonding the substantially relaxed layer to a substrate comprising an insulator; and
releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer,
wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
37. The method of claim 36 , wherein releasing the second etch-stop layer comprises a wet etch.
38. The method of claim 36 , further comprising:
releasing the substantially relaxed layer by removing at least a portion of the second etch-stop layer.
39. The method of claim 36 , wherein releasing the substantially relaxed layer comprises a wet etch.
40. A method for forming a semiconductor structure, the method comprising:
forming a first uniform etch-stop layer;
forming a second etch-stop layer over the uniform etch-stop layer; and
forming a substantially relaxed layer over the second etch-stop layer,
forming a substantially relaxed graded layer,
wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 , and the first uniform etch-stop layer is formed on the graded layer.
41. The method of claim 40 , wherein the substantially relaxed graded layer comprises Si 1−x Ge x .
42. The method of claim 40 , further comprising:
bonding the substantially relaxed layer to a substrate comprising an insulator.
43. The method of claim 40 , further comprising:
releasing the first etch-stop layer by removing at least a portion of the relaxed graded layer.
44. The method of claim 43 ,
wherein releasing the first etch-stop layer comprises a wet etch.
45. The method of claim 43 , further comprising:
releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer.
46. The method of claim 45 , further comprising:
releasing the relaxed layer by removing at least a portion of the second etch-stop layer.
47. The method of claim 46 , wherein releasing the relaxed layer comprises a wet etch.
48. The method of claim 43 , wherein releasing the second etch-stop layer comprises a wet etch.
49. A method for forming a semiconductor structure, the method comprising:
providing a first substrate; and
forming a layer structure over the first substrate by:
forming a substantially relaxed graded layer over the first substrate,
forming a first uniform etch-stop layer over the graded layer,
forming a second etch-stop layer over the uniform etch-stop layer, and
forming a substantially relaxed layer over the second etch-stop layer,
wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 , and the layer structure comprises the substantially relaxed graded layer, the first uniform etch-stop layer, the second etch-stop layer, and the substantially relaxed layer.
50. The method of claim 49 , wherein the substantially relaxed graded layer comprises Si 1−x Ge x .
51. The method of claim 49 , wherein the first uniform etch-stop layer comprises substantially relaxed Si 1−y G y , the second etch-stop layer comprises strained Si 1−z Ge z , 0≦z<1, and the substantially relaxed layer comprises Si 1−w Ge w .
52. The method of claim 49 , further comprising:
bonding the layer structure to a second substrate including an insulator.
53. The method of claim 52 , wherein the second substrate comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.
54. The method of claim 49 , the method further comprising:
releasing the first etch-stop layer by removing at least a portion of the first substrate and at least a portion of the graded layer; and
releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer.
55. The method of claim 54 , further comprising:
bonding the layer structure to a second substrate prior to releasing the first etch-stop layer.
56. The method of claim 54 , further comprising:
releasing at least a portion of the relaxed layer by removing at least a portion of the second etch-stop layer.
57. A method for forming a semiconductor structure, the method comprising:
providing a first substrate;
forming a layer structure on the first substrate by:
forming a substantially relaxed graded layer on the first substrate; and
forming a uniform etch-stop layer on the graded layer; and
releasing the etch-stop layer by removing at least a portion of the substrate and at least a portion of the graded layer,
wherein the uniform etch-stop layer of Si 1−y Ge y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 borons/cm 3 .
58. The method of claim 57 , wherein the substantially relaxed graded layer comprises Si 1−x Ge x .
59. The method of claim 57 , wherein the uniform etch-stop layer comprises substantially relaxed Si 1−y Ge y .
60. The method of claim 57 , further comprising:
bonding the layer structure to a second substrate prior to releasing the etch-stop layer.
61. A semiconductor structure comprising:
a layer structure including a uniform etch-stop layer having a doping level below 10 18 atoms/cm 3 ,
wherein the etch-stop layer comprises n-type dopants.
62. A semiconductor structure comprising:
a layer structure including a uniform etch-stop layer,
wherein the etch-stop layer comprises p-type dopants and the doping level is below 4×10 16 atoms/cm 3 .
63. A method for forming a semiconductor structure, the method comprising:
forming a layer structure including a uniform etch-stop layer;
providing a handle wafer; and
bonding the layer structure directly to the handle wafer,
wherein said uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×10 19 boron atoms/cm 3 .
64. A semiconductor structure comprising:
a layer structure comprising a uniform etch-stop layer, the etch-stop layer comprising SiGe and having a doping level below 10 18 atoms/cm 3 , and a substantially relaxed layer,
wherein the relaxed layer is graded.
65. A semiconductor structure comprising:
a layer structure comprising a uniform etch-stop layer, the etch-stop layer comprising SiGe and having a doping level below 10 18 atoms/cm 3 , and a substantially relaxed layer comprising Si 1−x Ge x ,
wherein the relaxed layer is graded and x<0.2.
66. A method for forming a semiconductor structure comprising:
providing a first substrate; and
forming a layer structure over the first substrate by:
forming a substantially relaxed graded layer over the first substrate, and forming a uniform etch-stop layer over the graded layer, the uniform etch-stop layer comprising SiGe and having a doping level below 10 18 atoms/cm 3 .