IP Library › Granted Patent US 7,227,490
Granted Patent B2
US 7,227,490 · App. 10/551,230 · Granted Jun 5, 2007

2-stage A/D converter and image sensor using the same

Assignee: National University Corporation Shizuoka University
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,227,490
App. No.
10/551,230
Granted
Jun 5, 2007
Kind
B2
Abstract

In a conventional CMOS image sensor, an A/D converter for performing A/D conversion at high-speed arranges the A/D converter elements in columns so as to operate in parallel, and has low resolution in the order of 9 or so bits. The present invention provides an A/D converter for an image sensor, which performs a part of the A/D conversion functions by using a noise cancellation circuit in columns and performs amplification simultaneously with this, thereby obtaining a high signal noise ratio (SNR) and implementing an A/D converter with a high resolution along with the A/D conversion section in a subsequent stage.

Claims (52)

1. A 2-stage A/D converter, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array and an amplifier for amplifying an analog residual which is a difference between an input signal and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the input signal by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein a predetermined value is subtracted from the input signal such that the output of the amplifier is controlled in a linear area without being saturated.

2. The 2-stage A/D converter according to claim 1 , wherein said amplifier performs G times amplification using a capacitance ratio of a capacitor, and the A/D conversion result is converted into an analog signal by switching a connection potential of one end of the capacitor of which the other end is connected to the input of said amplifier, and the output of said amplifier is controlled within a linear area without being saturated by subtracting said analog signal from the input signal, even if G times amplification is performed.

3. The 2-stage A/D converter according to claim 1 , wherein said amplifier is for performing G times amplification using a capacitance ratio of a capacitor, and in said N-bit A/D conversion, once a G times amplification operation is performed on a pixel signal, and the predetermined value is subtracted from the input signal using another capacitor when an output of said amplifier exceeds a reference voltage while the output of said amplifier and said reference voltage are sequentially compared by a comparator, so that the output of said amplifier is pulled back to a linear area even if the output of said amplifier is saturated, and the number of stages used to pull back the output of said amplifier to a predetermined voltage is regarded as the N-bit digital value, and the output of said amplifier after pull back is output as the analog residual.

4. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein a predetermined value is subtracted from the input signal such that the output of the amplifier is controlled in a linear area without being saturated.

5. The image sensor according to claim 4 , wherein said M-bit A/D conversion means for the analog residual performs the M-bit A/D conversion after horizontally scanning the analog values.

6. The image sensor according to claim 4 , wherein said M-bit A/D conversion means for the analog residual operates M bits of A/D conversion elements arranged in an array in columns.

7. The image sensor according to claim 4 , wherein said N-bit A/D conversion means comprises one comparator, a lamp signal generator common for columns, and a register for fetching a graycode value, which is supplied from outside a column, at the point when the output of the comparator changes.

8. The image sensor according to claim 4 , wherein said N-bit A/D conversion means for the pixel output performs A/D conversion using a 1-bit comparator, said amplifier performs G times amplification in columns using the capacitance ratio of the capacitor, and by connecting one end of the capacitor to an input of said amplifier, and the other end of the capacitor to a reference voltage at reset, and changing said reference voltage to determine the operation point of the output voltage of the amplifier by the output of said 1-bit comparator, the output of said amplifier is controlled within a linear area without being saturated, even if G times amplification is performed.

9. The image sensor according to claim 4 , wherein said amplifier has a function to acquire the difference between the pixel output of the reset level and the pixel output of the signal level, and performs noise cancellation by the function.

10. A 2-stage A/D converter, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array and an amplifier for amplifying an analog residual which is a difference between an input signal and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the input signal by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said amplifier performs G times amplification using a capacitance ratio of a capacitor, and the A/D conversion result is converted into an analog signal by switching a connection potential of one end of the capacitor of which the other end is connected to the input of said amplifier, and the output of said amplifier is controlled within a linear area without being saturated by subtracting said analog signal from the input signal, even if G times amplification is performed.

11. A 2-stage A/D converter, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array and an amplifier for amplifying an analog residual which is a difference between an input signal and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the input signal by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said amplifier is for performing G times amplification using a capacitance ratio of a capacitor, and in said N-bit A/D conversion, once a G times amplification operation is performed on a pixel signal, and the predetermined value is subtracted from the input signal using another capacitor when an output of said amplifier exceeds a reference voltage while the output of said amplifier and said reference voltage are sequentially compared by a comparator, so that the output of said amplifier is pulled back to a linear area even if the output of said amplifier is saturated, and the number of stages used to pull back the output of said amplifier to a predetermined voltage is regarded as the N-bit digital value, and the output of said amplifier after pull back is output as the analog residual.

12. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said M-bit A/D conversion means for the analog residual performs the M-bit A/D conversion after horizontally scanning the analog values.

13. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said M-bit A/D conversion means for the analog residual operates M bits of A/D conversion elements arranged in an array in columns.

14. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said N-bit A/D conversion means comprises one comparator, a lamp signal generator common for columns, and a register for fetching a graycode value, which is supplied from outside a column, at the point when the output of the comparator changes.

15. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said N-bit A/D conversion means for the pixel output performs A/D conversion using a 1-bit comparator, said amplifier performs G times amplification in columns using the capacitance ratio of the capacitor, and by connecting one end of the capacitor to an input of said amplifier, and the other end of the capacitor to a reference voltage at reset, and changing said reference voltage to determine the operation point of the output voltage of the amplifier by the output of said 1-bit comparator, the output of said amplifier is controlled within a linear area without being saturated, even if G times amplification is performed.

16. An image sensor, comprising:

an element circuit comprising N-bit A/D conversion means arranged in an array, and an amplifier for amplifying an analog residual which is a difference between a pixel output and an N-bit A/D conversion result; and

M-bit A/D conversion means for performing A/D conversion on said analog residual,

wherein an A/D conversion in a first stage is performed on the pixel output in columns of the image sensor by the N-bit A/D conversion means, and an A/D conversion in a second stage is performed on the amplified analog residual by the M-bit A/D conversion means, so as to perform N+M bit A/D conversion, and

wherein said amplifier has a function to acquire the difference between the pixel output of the reset level and the pixel output of the signal level, and performs noise cancellation by the function.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2005
From: KAWAHITO, SHOJI
To: NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY
Reel/Frame 017853/0227 →
Priority Claims (1)
JP 2003-093386 · Mar 31, 2003 · national
Continuity (1)
Related Publication 20060176205A1 · Aug 10, 2006