Oscillator of semiconductor device
An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.
1. An oscillator of a semiconductor memory device, the oscillator comprising:
a reference voltage generator for generating a reference voltage in such a way that the reference voltage shifts corresponding to a shift in a power supply voltage, wherein
the oscillator compares the reference voltage with a voltage generated according to a predetermined RC delay value, and generates a reference clock according to the comparison result, and
the reference voltage generator is enabled by an enable bar signal.
2. An oscillator of a semiconductor memory device, comprising:
a first voltage generator for generating a first voltage according to a first RC delay value;
a second voltage generator for generating a second voltage according to a second RC delay value;
a reference voltage generator for generating a reference voltage that shifts corresponding to a shift in a power supply voltage;
a first comparator for comparing the first voltage and the reference voltage;
a second comparator for comparing the second voltage and the reference voltage; and
logic combination units for latching output signals of the first and second comparators to generate a reference clock;
wherein the reference voltage generator is enabled by an enable bar signal.
3. The oscillator as claimed in claim 2 , wherein the reference voltage generator generates the reference voltage by dividing the power supply voltage.
4. The oscillator as claimed in claim 2 , wherein the reference voltage generator comprises:
a PMOS transistor that operates according to the enable bar signal; and
first and second resistors for dividing the power supply voltage transferred through the PMOS transistor to generate the reference voltage.
5. The oscillator as claimed in claim 2 , wherein the first voltage generator comprises:
an inverter for inverting an output signal of a first one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the first voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
6. The oscillator as claimed in claim 2 , wherein the second voltage generator comprises:
an inverter for inverting an output signal of a second one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the second voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
7. The oscillator as claimed in claim 2 , wherein the first and second comparators are enabled by the enable bar signal.
8. The oscillator as claimed in claim 2 , wherein each of the logic combination units is composed of a SR latch.
9. An oscillator, comprising:
a first voltage generator for generating a first voltage according to a first RC delay value;
a second voltage generator for generating a second voltage according to a second RC delay value;
a reference voltage generator for generating a reference voltage that shifts corresponding to a shift in a power supply voltage;
a first comparator for comparing the first voltage and the reference voltage;
a second comparator for comparing the second voltage and the reference voltage; and
logic combination units for latching output signals of the first and second comparators to generate a reference clock,
wherein the reference voltage generator is enabled by an enable bar signal.
10. The oscillator as claimed in claim 9 , wherein the reference voltage generator generates the reference voltage by dividing the power supply voltage.
11. The oscillator as claimed in claim 9 , wherein the reference voltage generator comprises:
a PMOS transistor that operates according to the enable bar signal; and
first and second resistors for dividing the power supply voltage transferred through the PMOS transistor to generate the reference voltage.
12. The oscillator as claimed in claim 9 , wherein the first voltage generator comprises:
an inverter for inverting an output signal of a first one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the first voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
13. The oscillator as claimed in claim 9 , wherein the second voltage generator comprises:
an inverter for inverting an output signal of a second one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the second voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
14. The oscillator as claimed in claim 9 , wherein the first and second comparators are enabled by the enable bar signal.
15. The oscillator as claimed in claim 9 , wherein each of the logic combination units is composed of a SR latch.
16. A semiconductor device, comprising:
an oscillator, comprising:
a reference voltage generator for generating a reference voltage in such a way that the reference voltage shifts corresponding to a shift in a power supply voltage;
wherein the oscillator compares the reference voltage with a voltage generated according to a predetermined RC delay value, and generates a reference clock according to the comparison result; and
wherein the reference voltage generator is enabled by an enable bar signal.
17. A semiconductor device, comprising:
an oscillator, comprising:
a first voltage generator for generating a first voltage according to a first RC delay value;
a second voltage generator for generating a second voltage according to a second RC delay value;
a reference voltage generator for generating a reference voltage that shifts corresponding to a shift in a power supply voltage;
a first comparator for comparing the first voltage and the reference voltage;
a second comparator for comparing the second voltage and the reference voltage; and
logic combination units for latching output signals of the first and second comparators to generate a reference clock;
wherein the reference voltage generator is enabled by an enable bar signal.
18. The device as claimed in claim 17 , wherein the reference voltage generator generates the reference voltage by dividing the power supply voltage.
19. The device as claimed in claim 17 , wherein the reference voltage generator comprises:
a PMOS transistor that operates according to the enable bar signal; and
first and second resistors for dividing the power supply voltage transferred through the PMOS transistor to generate the reference voltage.
20. The device as claimed in claim 17 , wherein the first voltage generator comprises:
an inverter for inverting an output signal of a first one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the first voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
21. The device as claimed in claim 17 , wherein the second voltage generator comprises:
an inverter for inverting an output signal of a second one of the logic combination units;
a resistor connected between a PMOS transistor of the inverter and an output terminal from which the second voltage is output; and
a capacitor connected to the output terminal and a ground voltage source.
22. The device as claimed in claim 17 , wherein the first and second comparators are enabled by the enable bar signal.
23. The device as claimed in claim 17 , wherein each of the logic combination units is composed of a SR latch.