Capacitor having an anodic metal oxide substrate

1. An electronic assembly, comprising:

an integrated circuit chip; and

a capacitor coupled to the intergated circuit chip, the capacitor comprising:

a metal plate including at least an anodized portion having a surface with a plurality of nanopores; an oxide layer formed on the surface and in the plurality of nanopores; and a metal core;

a plurality of nanowires disposed in the plurality of nanopores;

a conductive layer formed on the surface and attached to the plurality of nanowires;

at least one first terminal electrically coupled to the metal core;

at least one second terminal electrically coupled to the conductive layer;

a plurality of protective coatings formed on the core metal and disposed within the anodized portion;

the at least one first terminal includes a plurality of the first terminals formed within a plurality of openings in the protective coatings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

2. The electronic assembly according to claim 1 , wherein the plurality of protective coatings are uniformly distributed on the surface of the anodized portion.

3. An electronic assembly comprising:

an integrated circuit chip; and

a capacitor coupled to the integrated circuit chip, the capacitor comprising:

a metal plate including at least an anodized portion having a surface with a plurality of nanopores; an oxide layer formed on the surface and in the plurality of nanopores; and a metal core;

a plurality of nanowires disposed in the plurality of nanopores;

a conductive layer formed on the surface and attached to the plurality of nanowires;

at least one first terminal electrically coupled to the metal core;

at least one second terminal electrically coupled to the conductive layer;

a protective coating formed on the metal core and disposed within the anodized portion, with the protective coating including a first plurality of openings arranged to expose the metal core with each of the first plurality of openings containing a signal via;

the protective coating including a second plurality of openings arranged to expose the metal core, with the at least one first terminal includes a plurality of the first terminals formed within the second plurality of openings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

4. The electronic assembly according to claim 3 , wherein the first plurality of openings are uniformly distributed on the surface of the anodized portion.

5. An electronic assembly, comprising:

an integrated circuit chip; and

a capacitor coupled to the integrated circuit chip, the capacitor comprising:

a metal plate including at least and anodized portion having a surface with a plurality of nanopores; an oxide layer formed on the surface and in the plurality of nanopores; and a metal core;

a plurality of nanowires disposed in the plurality of nanopores;

a conductive layer formed on the surface and attached to the plurality of nanowires;

at least one first terminal electrically coupled to the metal core;

at least one second terminal electrically coupled to the conductive layer; and

wherein the metal plate comprises an anodic metal oxide substrate having a metal core, a pair of opposed surfaces with the plurality of nanopores disposed to extend between the opposed surfaces and to traverse the metal core; and an oxide layer formed on the opposed surfaces and in the plurality of nanopores.

6. The electronic assembly according to claim 5 , further comprising:

a plurality of protective coatings formed on the metal core and disposed on the pair of opposed surfaces;

the at least one first terminal includes a plurality of the first terminals formed within a plurality of openings in the protective coatings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

7. The electronic assembly according to claim 5 , further comprising:

a protective coating formed on the metal core and disposed on the pair of opposed surfaces, the protective coating including a first plurality of openings arranged to expose the metal core with each of the first plurality of openings containing a signal via;

the protective coating including a second plurality of openings arranged to expose the metal core, with the at least one first terminal includes a plurality of the first terminals formed within the second plurality of openings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

8. The electronic assembly according to claim 7 , wherein an input/output conductor is disposed in each of the signal vias.

9. The electronic assembly according to claim 1 , further comprising a chip carrier coupled to the integrated circuit chip and the capacitor.

10. The electronic assembly according to claim 3 , further comprising a chip carrier coupled to the integrated circuit chip and the capacitor.

11. The electronic assembly according to claim 5 , further comprising a chip carrier coupled to the integrated circuit chip and the capacitor.

12. The electronic assembly according to claim 5 , further comprising a laminated layer including the capacitor; and the laminated layer being laminated to the chip carrier.