IP Library › Granted Patent US 7,245,686
Granted Patent B2
US 7,245,686 · App. 10/320,766 · Granted Jul 17, 2007

Fast skew detector

Assignee: Mysticom Ltd.
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Quick Facts
Patent No.
US 7,245,686
App. No.
10/320,766
Granted
Jul 17, 2007
Kind
B2
Abstract

Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval. The apparatus includes a predictor, which determines, for each of the symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, and logic, which compares the expected value with the at least one bit of each of the second symbols in the FIFO, so as to determine a relative skew between the first and at least the second channel.

Claims (41)

1. A data receiver for receiving communication signals from a transmitter over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, said data receiver comprising:

an input circuit, which is coupled to process the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;

a first-in-first-out (FIFO) memory, which is coupled to the input circuit so as to receive and store at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;

a symbol predictor, which is adapted, based on the predetermined relation between the first and second symbols, to determine for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval; and

comparison logic, which is adapted to compare the expected value with the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a relative skew between the first and at least the second channel, wherein the comparison logic generates, for each comparison performed by the logic, one of a matched and a non-matched result, and wherein the logic comprises an elimination memory array wherein are stored the results of the comparisons,

wherein the comparison logic is adapted to perform iterations of the comparisons performed by the logic, wherein for each iteration the logic compares the expected value with the at least one bit of each of the received second symbols generating the matched result in a previous comparison,

wherein the comparison logic is adapted to perform the iterations until only one matched result remains in the elimination array, and wherein the relative skew is determined from a position of the one matched result in the elimination array.

2. Apparatus according to claim 1 , wherein the FIFO memory comprises a first column wherein are stored sequentially the at least one bit of each of the received symbols of the first sequence, and at least one second column wherein are stored sequentially and respectively the at least one bit of each of the received symbols of the at least one second sequence, and wherein for each iteration the comparison logic is adapted to sequentially advance the at least one bit of the first column and the at least one bit of the at least one second column, so as to generate for the symbol predictor the received symbol in the first interval and the at least one bit in the corresponding one of the second symbols in the second interval.

3. Apparatus according to claim 1 , wherein the at least one second channel comprises three channels.

4. Apparatus according to claim 1 , wherein each of the symbols comprises a plurality of levels, and wherein the input circuit is adapted to translate the levels to unique bit strings.

5. Apparatus according to claim 1 , wherein the data receiver and the transmitter communicate via a communication protocol which defines a maximum value of the relative skew, and wherein the first interval and the second interval are respective predetermined functions of the maximum value.

6. Apparatus according to claim 1 , wherein the data receiver and the transmitter communicate via a communication protocol which defines a maximum value of the relative skew, and wherein an overlap between the first interval and the second interval is a predetermined function of the maximum value.

7. A data receiver for receiving communication signals from a transmitter over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, said data receiver comprising:

an input circuit, which is coupled to process the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;

a first-in-first-out (FIFO) memory, which is coupled to the input circuit so as to receive and store at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;

a symbol predictor, which is adapted, based on the predetermined relation between the first and second symbols, to determine for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval; and

comparison logic, which is adapted to compare the expected value with the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a relative skew between the first and at least the second channel,

wherein the transmitter and the data receiver are adapted to exist in a plurality of communication modes, and wherein the symbol predictor is adapted to generate a respective plurality of expected values, comprised in the expected value, in response to the communication modes, and wherein the comparison logic is adapted to determine a communicating state, comprised in the communication modes, responsive to comparisons between the respective plurality of expected values and the at least one bit of each of the received second symbols in the FIFO memory.

wherein the comparison logic generates, for each comparison performed by the logic, one of a matched and a non-matched result, and wherein the logic comprises an elimination memory array wherein are stored the results of the comparisons, and wherein the comparison logic is adapted to perform iterations of the comparisons, wherein for each iteration the logic compares the expected value with the at least one bit of each of the received second symbols generating the matched result in a previous comparison, and wherein the comparison logic is adapted to perform the iterations until only one matched result remains in the elimination array, and wherein the communicating state is determined from a position of the one matched result in the elimination array.

8. A method for receiving communication signals from a transmitter transmitted over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, comprising:

processing the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;

receiving and storing in a first-in-first-out (FIFO) memory at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;

determining for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, based on the predetermined relation between the first and second symbols; and

performing comparisons between the expected value and the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a relative skew between the first and at least the second channel,

and comprising generating, for each comparison performed, one of a matched and a non-matched result, and storing the results of the comparisons in an elimination memory array,

and comprising performing iterations of the comparisons, wherein in each iteration the comparison compares the expected value with the at least one bit of each of the received second symbols generating the matched result in a previous comparison,

and comprising performing the iterations until only one matched result remains in the elimination memory array, and wherein the relative skew is determined from a position of the one matched result in the elimination memory array.

9. A method according to claim 8 , wherein the FIFO memory comprises a first column wherein are stored sequentially the at least one bit of each of the received symbols of the first sequence, and at least one second column wherein are stored sequentially and respectively the at least one bit of each of the received symbols of the at least second sequence, and for each iteration sequentially advancing the at least one bit of the first column and the at least one bit of the at least one second column, so as to generate the received symbol in the first interval and the at least one bit in the corresponding one of the second symbols in the second interval.

10. A method for receiving communication signals from a transmitter transmitted over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, comprising:

processing the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;

receiving and storing in a first-in-first-out (FIFO) memory at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;

determining for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, based on the predetermined relation between the first and second symbols; and

performing comparisons between the expected value and the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a relative skew between the first and at least the second channel

wherein the transmitter is adapted to transmit the communication signals in a plurality of communication modes, and wherein determining for each of the received symbols in the first interval of the first sequence the expected value comprises generating a respective plurality of expected values, in response to the communication modes, and determining a communicating state, comprised in the communication modes, responsive to comparisons between the respective plurality of expected values and the at least one bit of each of the received second symbols in the FIFO memory, and comprising:

generating, for each comparison performed, one of a matched and a non-matched result;

storing the results of the comparisons in an elimination memory array; performing iterations of the comparisons, wherein each iteration comprises comparing the expected value with the at least one bit of each of the received second symbols that generated the matched result in a previous comparison, until only one matched result remains in the elimination array; and

determining the communicating state from a position of the one matched result in the elimination array.

11. A method according to claim 10 , wherein the at least one second channel comprises three channels.

12. A method according to claim 10 , wherein each of the symbols comprises a plurality of levels, and comprising translating the levels to unique bit strings.

13. A method according to claim 10 , wherein the communication signals are generated in response to a communication protocol which defines a maximum value of the relative skew, and wherein the first interval and the second interval are respective predetermined functions of the maximum value.

14. A method according to claim 10 , wherein the communication signals are generated in response to a communication protocol which defines a maximum value of the relative skew, and wherein an overlap between the first interval and the second interval is a predetermined function of the maximum value.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2014
From: MYSTICOM LTD.
To: CADENCE DESIGN SYSTEMS INC.
Reel/Frame 034429/0757 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2005
From: WEISS, RAMI; BUBLIL, BARUCH; GREISS, ISRAEL
To: MYSTICOM LTD.
Reel/Frame 017064/0836 →
Continuity (2)
Provisional Application 6034152600 · Dec 17, 2001
Related Publication 20030142772A1 · Jul 31, 2003