Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques
Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.
1. A method of fabricating a semiconductor integrated circuit, the method comprising:
forming an inter-layer insulating layer on a single-crystalline semiconductor substrate;
forming a single-crystalline semiconductor plug penetrating the inter-layer insulating layer;
forming a single-crystalline epitaxial semiconductor pattern covering the inter-layer insulating layer, the single-crystalline epitaxial semiconductor pattern being in contact with the single-crystalline semiconductor plug;
at least partially planarizing the single-crystalline epitaxial semiconductor pattern to form a semiconductor body layer on the inter-layer insulating layer; and
patterning the semiconductor body layer to form a semiconductor body.
2. The method according to claim 1 , wherein the single-crystalline semiconductor plug and the single-crystalline epitaxial semiconductor pattern are formed in-situ.
3. The method according to claim 1 , wherein forming the single-crystalline semiconductor plug and forming the single-crystalline epitaxial semiconductor pattern comprises:
patterning the inter-layer insulating layer to form a contact hole exposing the single-crystalline semiconductor substrate;
growing a doped single-crystalline epitaxial semiconductor layer filling the contact hole using an SEG technique that employs the exposed single-crystalline semiconductor substrate as a seed layer; and
forming a single-crystalline epitaxial semiconductor layer covering the doped single-crystalline epitaxial semiconductor layer and the inter-layer insulating layer using an SEG technique that employs the doped single-crystalline epitaxial semiconductor layer as a seed layer.
4. The method according to claim 3 , further comprising:
planarizing the doped single-crystalline epitaxial semiconductor layer before forming the single-crystalline epitaxial semiconductor layer covering the inter-layer insulating layer; and
cleaning a surface of the planarized single-crystalline epitaxial semiconductor layer.
5. The method according to claim 1 , wherein at least partially planarizing the single-crystalline epitaxial semiconductor pattern is performed by a CMP technique.
6. The method according to claim 1 , further comprising:
forming a non-single-crystalline semiconductor layer overlying the single-crystalline epitaxial semiconductor pattern before forming the semiconductor body layer; and
crystallizing the non-single-crystalline semiconductor layer using a solid phase epitaxial technique that employs the single-crystalline epitaxial semiconductor pattern as a seed layer,
wherein the semiconductor body layer is formed by at least partially planarizing the crystallized semiconductor layer and the single-crystalline epitaxial semiconductor pattern.
7. The method according to claim 6 , wherein the non-single-crystalline semiconductor layer comprises an amorphous semiconductor layer or a polycrystalline semiconductor layer.
8. The method according to claim 1 , further comprising:
forming a non-single-crystalline semiconductor layer overlying the single-crystalline epitaxial semiconductor pattern before forming the semiconductor body layer; and
performing a solid phase epitaxial process using the single-crystalline epitaxial semiconductor pattern as a seed layer before patterning the semiconductor body layer,
wherein the semiconductor body layer is formed by at least partially planarizing the non-single-crystalline semiconductor layer and the single-crystalline epitaxial semiconductor pattern, and the planarized non-single-crystalline semiconductor layer is crystallized during the solid phase epitaxial process.
9. The method according to claim 1 , further comprising forming a thin film transistor on the semiconductor body.
10. The method according to claim 9 , wherein forming the thin film transistor comprises:
forming a gate electrode extending across the semiconductor body, the gate electrode covering sidewalls of the semiconductor body; and
implanting impurity ions into the semiconductor body, using the gate electrode as an ion implantation mask, to form source and drain regions therein.
11. The method according to claim 1 , further comprising:
forming an isolation layer on a predetermined region of the single-crystalline semiconductor substrate to define an active region before forming the inter-layer insulating layer; and
forming a bulk metal oxide semiconductor (MOS) transistor in the active region,
wherein the bulk MOS transistor includes a gate electrode extending across the active region and source/drain regions located on both sides of a channel region below the gate electrode.
12. The method according to claim 11 , wherein the single-crystalline semiconductor plug is in contact with at least one of the source/drain regions of the bulk MOS transistor.
13. A method of fabricating a thin film transistor static random access memory (TFT SRAM) cell composed of first and second half-cells, the method of fabricating one of the first and second half-cells comprising:
forming an isolation layer on a predetermined region of a single-crystalline semiconductor substrate to define an active region;
forming a driver transistor at the active region, the driver transistor having a driver gate electrode extending across the active region and source/drain regions located on both sides of a channel region below the driver gate electrode;
forming an inter-layer insulating layer overlying the driver transistor;
forming a single-crystalline semiconductor plug penetrating the inter-layer insulating layer to contact the drain region of the driver transistor;
forming a single-crystalline epitaxial semiconductor pattern covering the inter-layer insulating layer, the single-crystalline epitaxial semiconductor pattern being in contact with the single-crystalline semiconductor plug;
planarizing the single-crystalline epitaxial semiconductor pattern to form a semiconductor body layer on the inter-layer insulating layer; and
patterning the semiconductor body layer to form a semiconductor body.
14. The method according to claim 13 , wherein forming the single-crystalline semiconductor plug and forming the single-crystalline epitaxial semiconductor pattern comprises:
patterning the inter-layer insulating layer to form a node contact hole exposing the drain region of the driver transistor; and
growing a single-crystalline epitaxial semiconductor layer that fills the node contact hole and covers the inter-layer insulating layer, using an SEG technique employing the exposed drain region as a seed layer.
15. The method according to claim 13 , wherein forming the single-crystalline semiconductor plug and forming the single-crystalline epitaxial semiconductor pattern comprises:
patterning the inter-layer insulating layer to form a node contact hole exposing the drain region of the driver transistor;
growing a doped single-crystalline epitaxial semiconductor layer filling the node contact hole, using an SEG technique employing the exposed drain region as a seed layer; and
forming a single-crystalline epitaxial semiconductor layer covering the doped single-crystalline epitaxial semiconductor layer and the inter-layer insulating layer using an SEG technique employing the doped single-crystalline epitaxial semiconductor layer as a seed layer.
16. The method according to claim 15 , further comprising:
planarizing the doped single-crystalline epitaxial semiconductor layer; and
cleaning a surface of the planarized single-crystalline epitaxial semiconductor layer.
17. The method according to claim 13 , wherein planarizing the single-crystalline epitaxial semiconductor pattern comprises CMP.
18. The method according to claim 13 , further comprising:
forming a non-single-crystalline semiconductor layer overlying the single-crystalline epitaxial semiconductor pattern before forming the semiconductor body layer; and
crystallizing the non-single-crystalline semiconductor layer using a solid phase epitaxial technique employing the single-crystalline epitaxial semiconductor pattern as a seed layer,
wherein the semiconductor body layer is formed by at least partially planarizing the crystallized semiconductor layer and the single-crystalline epitaxial semiconductor pattern.
19. The method according to claim 18 , wherein the non-single-crystalline semiconductor layer is formed of an amorphous semiconductor layer or a polycrystalline semiconductor layer.
20. The method according to claim 13 , further comprising:
forming a non-single-crystalline semiconductor layer overlying the single-crystalline epitaxial semiconductor pattern before forming the semiconductor body layer; and
performing a solid phase epitaxial process using the single-crystalline epitaxial semiconductor pattern as a seed layer before patterning the semiconductor body layer,
wherein the semiconductor body layer is formed by at least partially planarizing the non-single-crystalline semiconductor layer and the single-crystalline epitaxial semiconductor pattern, and the planarized non-single-crystalline semiconductor layer is crystallized during the solid phase epitaxial process.
21. The method according to claim 13 , further comprising forming a load thin film transistor serving as a load transistor at the semiconductor body,
wherein the load thin film transistor includes a load gate electrode extending across the semiconductor body and covering sidewalls of the semiconductor body, a drain region adjacent to the load gate electrode and located on the single-crystalline semiconductor plug, and a source region adjacent to the load gate electrode and located opposite to the drain region.
22. The method according to claim 21 , further comprising:
forming a second inter-layer insulating layer over the load thin film transistor;
forming a second single-crystalline semiconductor plug penetrating the second inter-layer insulating layer to be in contact with the drain region of the load thin film transistor and a second single-crystalline epitaxial semiconductor pattern covering the second inter-layer insulating layer, the second single-crystalline epitaxial semiconductor pattern being in contact with the second single-crystalline semiconductor plug;
at least partially planarizing the second single-crystalline epitaxial semiconductor pattern to form a second semiconductor body layer on the second inter-layer insulating layer; and
patterning the second semiconductor body layer to form a second semiconductor body that is in contact with the second single-crystalline semiconductor plug.
23. The method according to claim 22 , wherein forming the second single-crystalline semiconductor plug and the second single-crystalline epitaxial semiconductor pattern comprises:
patterning the second inter-layer insulating layer to form a second node contact hole exposing the drain region of the load thin film transistor; and
growing a single-crystalline epitaxial semiconductor layer filling the second node contact hole and covering the second inter-layer insulating layer using an SEG technique that employs the exposed drain region as a seed layer.
24. The method according to claim 22 , wherein forming the second single-crystalline semiconductor plug and the second single-crystalline epitaxial semiconductor pattern comprises:
patterning the second inter-layer insulating layer to form a second node contact hole exposing the drain region of the load thin film transistor;
growing a doped single-crystalline epitaxial semiconductor layer filling the second node contact hole using an SEG technique that employs the exposed drain region as a seed layer; and
forming a single-crystalline epitaxial semiconductor layer covering the doped single-crystalline epitaxial semiconductor layer and the second inter-layer insulating layer using a SEG technique that employs the doped single-crystalline epitaxial semiconductor layer as a seed layer.
25. The method according to claim 24 , further comprising:
planarizing the doped single-crystalline epitaxial semiconductor layer; and
cleaning a surface of the planarized single-crystalline epitaxial semiconductor layer.
26. The method according to claim 22 , wherein planarizing the second single-crystalline epitaxial semiconductor pattern comprises CMP.
27. The method according to claim 22 , further comprising:
forming a second non-single-crystalline semiconductor layer overlying the second single-crystalline epitaxial semiconductor pattern before forming the second semiconductor body layer; and
crystallizing the second non-single-crystalline semiconductor layer using a solid phase epitaxial technique that employs the second single-crystalline epitaxial semiconductor pattern as a seed layer,
wherein the second semiconductor body layer is formed by at least partially planarizing the crystallized semiconductor layer and the second single-crystalline epitaxial semiconductor pattern.
28. The method according to claim 27 , wherein the second non-single-crystalline semiconductor layer is formed of an amorphous semiconductor layer or a polycrystalline semiconductor layer.
29. The method according to claim 22 , further comprising:
forming a second non-single-crystalline semiconductor layer over the second single-crystalline epitaxial semiconductor pattern before forming the second semiconductor body layer; and
performing a solid phase epitaxial process employing the second single-crystalline epitaxial semiconductor pattern as a seed layer before patterning the second semiconductor body layer,
wherein the second semiconductor body layer is formed by at least partially planarizing the second non-single-crystalline semiconductor layer and the second single-crystalline epitaxial semiconductor pattern, and the planarized non-single-crystalline semiconductor layer is crystallized during the solid phase epitaxial process.
30. The method according to claim 22 , further comprising forming a transfer thin film transistor serving as a transfer transistor on the second the semiconductor body,
wherein the transfer thin film transistor includes a transfer gate electrode extending across the second semiconductor body and covering both sidewalls of the second semiconductor body, a source region adjacent to the transfer gate electrode and located on the second single-crystalline semiconductor plug, and a drain region adjacent to the transfer gate electrode and located opposite to the source region.
31. The method according to claim 30 , further comprising:
forming a third inter-layer insulating layer overlying the transfer thin film transistor; and
forming a node metal plug penetrating the first to third inter-layer insulating layers,
wherein the node metal plug is formed of a metal layer having an ohmic contact with the drain region of the driver transistor, the single-crystalline semiconductor plug, the drain region of the load thin film transistor, the second single-crystalline semiconductor plug, and the source region of the transfer thin film transistor.
32. The method according to claim 21 , further comprising forming a transfer transistor in the active region during formation of the driver transistor,
wherein the transfer transistor comprises a transfer gate electrode extending across the active region as well as source/drain regions located on both sides of a channel region below the transfer gate electrode, and the source region of the transfer transistor corresponds to the drain region of the driver transistor.
33. The method according to claim 32 , further comprising:
forming a second inter-layer insulating layer on the substrate having the load thin film transistor; and
forming a node metal plug penetrating the first and second inter-layer insulating layers,
wherein the node metal plug is formed of a metal layer having an ohmic contact with the drain region of the driver transistor, the single-crystalline semiconductor plug, and the drain region of the load thin film transistor.