Multi-threshold MOS circuits

1. An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:

a master latch comprised of low threshold (LVT) transistors;

a slave latch operative to sample and hold output data from the master latch for the multi-threshold flip-flop and comprised of first and second inverters formed with high threshold (HVT) transistors and coupled in a feedback configuration, and

first and second pass switches formed with HVT transistors, the first pass switch being coupled to an input of the first inverter, and the second pass switch being coupled within the feedback configuration; and

at least one control switch operative to enable or disable the LVT transistors.

2. The integrated circuit of claim 1 , wherein the master latch for each multi-threshold flip-flop comprises

a latch circuit comprised of LVT transistors and operative to sample and hold input data, and

wherein the at least one control switch is operative to enable or disable the LVT transistors for the latch circuit.

3. The integrated circuit of claim 2 , wherein the latch circuit in the master latch for each multi-threshold flip-flop comprises

first and second inverters formed with LVT transistors and coupled in a feedback configuration, and

first and second pass switches formed with LVT transistors, the first pass switch being coupled to an input of the first inverter and the second pass switch being coupled within the feedback configuration.

4. The integrated circuit of claim 2 , wherein the master latch for each multi-threshold flip-flop further comprises

an input buffer comprised of LVT transistors and operative to buffer the input data and provide buffered data to the latch circuit, and wherein the at least one control switch is operative to enable or disable the LVT transistors for the input buffer.

5. The integrated circuit of claim 1 wherein the slave latch for each multi-threshold flip-flop further comprises

an output driver formed with LVT transistors and operative to provide signal drive for the multi-threshold flip-flop, and wherein the at least one control switch is operative to enable or disable the LVT transistors for the output driver.

6. The integrated circuit of claim 5 , wherein the at least one control switch for each multi-threshold flip-flop comprises

a first set of at least one footswitch configured to receive a first enable signal and operative to enable or disable the LVT transistors for the master latch based on the first enable signal, and

a second set of at least one footswitch configured to receive a second enable signal and operative to enable or disable the LVT transistors for the output driver based on the second enable signal.

7. The integrated circuit of claim 1 , wherein the slave latch for each multi-threshold flip-flop further comprises

a pull-up transistor operative to pull an output of the multi-threshold flip-flop to a known logic state when the multi-threshold flip-flop is disabled.

8. The integrated circuit of claim 1 , wherein the slave latch for each multi-threshold flip-flop is operative to retain a logic state of the multi-threshold flip-flop when the multi-threshold flip-flop is disabled.

9. The integrated circuit of claim 1 , wherein the at least one multi-threshold flip-flop is operative to receive a clock signal that is maintained at a predetermined logic level when the least one multi-threshold flip-flop is disabled.

10. The integrated circuit of claim 1 , wherein the at least one control switch comprises at least one footswitch.

11. The integrated circuit of claim 1 , wherein the at least one control switch comprises at least one headswitch.

12. The integrated circuit of claim 1 , wherein the least one control switch is formed with at least one HVT transistor.

13. The integrated circuit of claim 1 , wherein the LVT transistors and the HVT transistors are metal oxide semiconductor (MOS) devices.

14. An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:

a master latch comprised of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors;

a slave latch operative to sample and hold output data from the master latch for the multi-threshold flip-flop and comprised of

a second latch circuit comprising first and second inverters formed with high threshold (HVT) transistors and coupled in a feedback configuration,

first and second pass switches formed with HVT transistors, the first pass switch being coupled to an input of the first inverter, and the second pass switch being coupled within the feedback configuration, and

an output driver formed with LVT transistors; and

at least one control switch operative to enable or disable the LVT transistors for the input buffer, the first latch circuit, and the output driver.

15. The integrated circuit of claim 14 , wherein the slave latch for each multi-threshold flip-flop is operative to retain a logic state of the multi-threshold flip-flop when the multi-threshold flip-flop is disabled.

16. The integrated circuit of claim 14 , wherein the least one control switch for each multi-threshold flip-flop is formed with at least one HVT transistor.

17. The integrated circuit of claim 14 , wherein the LVT transistors and the HVT transistors are N-channel field effect transistors (N-FLTs), P-channel field effect transistors (P-FETs), or a combination thereof.