Semiconductor device that initializes memory cells of an activated wordline group
A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value during an initial value setting operation; a first power supply circuit, which supplies power to bitlines in response to the first control signal; a second power supply circuit, which supplies power to complementary bitlines in response to the second control signal; a plurality of wordlines connected to respective memory cells; and a row decoder, which selects a group of wordlines from among the plurality of wordlines based on the setting signal and a selection address and simultaneously activates the selected group of wordlines.
1. A semiconductor device comprising:
a control signal generation circuit, which generates first and second control signals in response to an activated setting signal and an initial data value during an initial value setting operation;
a first power supply circuit, which supplies power to bitlines in response to the first control signal;
a second power supply circuit, which supplies power to complementary bitlines in response to the second control signal;
a plurality of wordlines connected to a plurality of memory cells; and
a row decoder, which selects a group of wordlines from the plurality of wordlines in response to the setting signal and a selection address and activates the selected group of wordlines.
2. The semiconductor device of claim 1 , wherein the first and second control signals generated by the control signal generation circuit are not activated at the same time.
3. The semiconductor device of claim 1 , wherein the selection address comprises a most significant bit (MSB) of a row address input to the row decoder.
4. The semiconductor device of claim 1 , wherein a number K of wordlines selected in response to the setting signal and the selection address is determined by using the following equation;
where M is a total number of wordlines, and N is the size in bits of the selection address.
5. The semiconductor device of claim 1 , wherein the first power supply circuit and the second power supply circuit each include a PMOS transistor.
6. The semiconductor device of claim 1 , wherein the memory cells are SRAM cells.
7. The semiconductor device of claim 1 , wherein the control signal generation circuit and row decoder are connected to a controller for generating me activated setting signal, initial data value and selection address.
8. A semiconductor device comprising a plurality of memory cells connected to M wordlines, the semiconductor device comprising:
a control signal generation circuit, which generates first and second control signals in response to an activated setting signal and an initial data value during an initial value setting operation;
a first power supply, which precharges bitlines to a power supply voltage level in response to the first control signal;
a second power supply, which precharges complementary bitlines to the power supply voltage level in response to the second control signal; and
a row decoder, which activates groups of wordlines based on the setting signal and a selection address, each of the groups of wordlines comprising M/2 N wordlines where N is a total number of wordlines in the semiconductor device, and N is the size in bits of the selection address.
9. The semiconductor device of claim 8 , wherein the selection address comprises a most significant bit (MSB) of a row address and bits of the row address that are subsequent to the MSB.
10. The semiconductor device of claim 8 , wherein the first and second control signals generated by the control signal generation circuit are not activated at the same time.
11. The semiconductor device of claim 8 , wherein the groups of wordlines are sequentially activated.
12. The semiconductor device of claim 8 , wherein the control signal generation circuit and row decoder are connected to a controller for generating the activated setting signal, initial data value and selection address and a busy signal for indicating that the initial value setting operation is being performed.
13. The semiconductor device of claim 8 , wherein the memory cells are SRAM cells.
14. A method for initializing memory cells, comprising:
generating, at a control signal generation circuit, first and second control signals in response to an activated setting signal and an initial data value during an initial value setting operation;
supplying, at a first power supply circuit, power to bitlines in response to the first control signal;
supplying, at a second power supply circuit, power to complementary bitlines, in response to the second control signal; and
selecting, at a row decoder, a group of wordlines from a plurality of wordlines in response to the setting signal and a selection address and simultaneously activating the selected group of wordlines.
15. The method of claim 14 , wherein the first and second control signals are not activated at the same time.
16. The method of claim 14 , wherein the selection address comprises a most significant bit (MSB) of a row address input to the row decoder.
17. The method of claim 14 , wherein a number K of wordlines selected in response to the setting signal and the selection address is determined by using the following equation:
K
=
M
2
N
where M is a total number of wordlines, and N is the size in bits of the selection address.