Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
1. A method, comprising:
forming a first transistor in a substrate;
forming a second transistor in the substrate having a shared source/drain region with the first transistor;
forming a barrier in the shared region; and
forming a non-conducting region between a drain region of the first transistor and a source region of the second transistor in a portion of a doped well, wherein the width of the non-conductive region is adjusted to provide a specified breakdown voltage of a parasitic feature.
2. The method of claim 1 , wherein forming the barrier includes removing a portion of the shared region and inserting a non-conductive material in the portion of the shared region.
3. The method of claim 2 , wherein removing the portion of the shared region includes etching the shared region.
4. The method of claim 1 , wherein forming the first transistor includes forming a MOS transistor.
5. The method of claim 4 , wherein forming the second transistor includes forming a MOS transistor.
6. The method of claim 4 , wherein forming the first transistor includes forming an active well in the substrate.
7. The method of claim 6 , wherein forming the barrier includes forming the barrier to extend into the active well in the substrate.
8. The method of claim 1 , wherein forming a non-conducting region includes forming the non-conductive region using the barrier.
9. The method of claim 8 , wherein the forming includes shaping the non-conductive region using the barrier and the well.
10. A method, comprising:
simultaneously forming a first transistor and a second transistor in a substrate such that the first and second transistors are in a cascode configuration with a shared region;
forming a barrier in the shared region; and
forming a non-conducting region between the first transistor and the second transistor in a portion of a doped well, wherein the width of the non-conductive region is adjusted to provide a specified breakdown voltage of a parasitic bipolar transistor.
11. The method of claim 10 , wherein forming the barrier includes removing a portion of the shared region and inserting a non-conductive material in the portion of the shared region.
12. The method of claim 11 , wherein removing the portion of the shared region includes etching the shared region.
13. The method of claim 10 , wherein forming the first transistor includes forming a MOS transistor.
14. The method of claim 13 , wherein forming the second transistor includes forming a MOS transistor.
15. The method of claim 13 , wherein forming the first transistor includes forming an active well in the substrate.
16. The method of claim 15 , wherein forming the barrier includes forming the barrier to extend into the active well in the substrate.
17. A method, comprising:
forming a doped region having a first conductivity type in a substrate;
forming a set of cascode-connected transistors having channels in the doped region;
forming a barrier in a shared region of the cascode-connected transistors; and
forming a non-conducting region between the set of cascode-connected transistors in a portion of a doped well, wherein the width of the non-conductive region is to provide a specified breakdown voltage of a parasitic feature.
18. The method of claim 17 , wherein forming the barrier includes removing a portion of the shared region and inserting a non-conductive material in the portion of the shared region.
19. The method of claim 18 , wherein removing the portion of the shared region includes etching the shared region.
20. The method of claim 17 , wherein forming a non-conducting region includes forming the non-conductive region using the barrier.
21. The method of claim 20 , wherein the forming includes shaping the non-conductive region using the barrier and the well.
22. A method, comprising:
forming a doped region having a first conductivity type in a substrate;
forming a set of cascode-connected transistors having channels in the doped region, wherein forming the set of transistors includes:
forming a first diffusion region having a second conductivity type in the doped region;
forming a second diffusion region having the second conductivity type in the doped region; and
forming a third diffusion region having the second conductivity type in the doped region;
forming a barrier in the second diffusion region; and
forming a non-conducting region between the set of cascode-connected transistors in a portion of a doped well, wherein forming the non-conducting region includes adjusting the width of the non-conductive region to provide a specified parasitic breakdown voltage.
23. The method of claim 22 , wherein forming the set of transistors includes masking a surface of the doped region to create openings, and supplying dopants through the openings to form the first, second, and third diffusion regions.
24. The method of claim 23 , wherein supplying dopants through the openings includes simultaneously supplying dopants through the openings to form the first, second, and third diffusion regions.
25. The method of claim 23 , wherein forming the barrier includes masking the second diffusion region after supplying dopants to the second region and etching an unmasked portion of the second diffusion region to form a well therein.
26. The method of claim 25 , wherein forming the barrier includes filling the well with a non-conductive material.
27. The method of claim 25 , wherein forming the barrier includes extending the barrier through the doped region.
28. The method of claim 23 , wherein supplying dopants includes supplying N-type dopants.
29. The method of claim 22 , wherein the first conductivity type is a P-type and the second conductivity type is an N-type.
30. A method, comprising:
forming a doped region having a first conductivity type in a substrate;
forming a set of cascode-connected transistors having channels in the doped region, wherein forming the set of transistors includes:
forming a first diffusion region in the doped region;
forming a second diffusion region in the doped region; and
forming a third diffusion region in the doped region; and
forming a barrier in the second diffusion region such that the barrier extends through the second diffusion region into the doped region, wherein forming a barrier includes forming the barrier with at least one of a width and a depth of the barrier being adjusted to provide a specified parasitic breakdown voltage.
31. The method of claim 30 , wherein forming the set of transistors includes masking a surface of the doped region to create openings, and supplying dopants through the openings to form the first, second, and third diffusion regions.
32. The method of claim 31 , wherein diffusing dopants through the openings includes simultaneously supplying dopants through the openings to form the first, second, and third diffusion regions.
33. The method of claim 31 , wherein supplying dopants includes supplying N-type dopants.
34. The method of claim 30 , wherein forming the barrier includes masking the second diffusion region after supplying dopants to the second region and etching an unmasked portion of the second diffusion region to form a well therein.
35. The method of claim 30 , wherein forming the barrier includes filling the well with a non-conductive material.
36. The method of claim 30 , wherein the first conductivity type is a P-type and the second conductivity type is an N-type.
37. A method for improving operation of a cascode-type driver in an output buffer of an integrated circuit, comprising:
inserting a gap in the common node of the cascode-connected transistors, wherein a width of the gap is used to adjust a breakdown voltage of a parasitic transistor.
38. The method of claim 37 , wherein inserting the gap includes extending the gap into an active well of a substrate.