Active matrix panel with two thin film transistors to a pixel
An active matrix panel comprises a semiconductor thin film to constitute the switching element which includes••a common source-drain region having a bend portion with a channel region on one end and the other end further followed by a second source region of the channel region sequentially formed to one end of the common source-drain region and a second drain region of the channel region sequentially formed to the other end of the common source-drain which is connected to one of the data lines; a gate insulating film arranged on a surface of the semiconductor thin film; and a gate electrode arranged in areas on the gate insulating film corresponding to the channel region upper part for the second source region and the second drain region which is connected to one of the scanning lines.
1. An active matrix panel comprising:
a plurality of scanning lines;
a plurality of data lines; and
a plurality of switching elements which are individually connected to the scanning lines and the data lines;
the switching elements respectively comprising:
a semiconductor thin film a semiconductor thin film••which includes:••
a common source-drain region having a bend portion with a channel region on one end and the other end further followed by a second source region of the channel region sequentially formed to one end of the common source-drain region and a second drain region of the channel region sequentially formed to the other end of the common source-drain which is connected to one of the data lines;
a gate insulating film arranged on a surface of the semiconductor thin film; and
a gate electrode arranged in areas on the gate insulating film corresponding to the channel region upper part for the second source region and the second drain region which is connected to one of the scanning lines.
2. The active matrix panel according to claim 1 , wherein the gate electrode includes a first electrode which traverses the channel region of second source region at a right angle and a second electrode which traverses the channel region of the second drain region at a right angle as well as the first electrode and the second gate electrode being sequentially formed.
3. The active matrix panel according to claim 1 , wherein the gate electrode includes a bend portion where the first electrode and the second electrode join together.
4. The active matrix panel according to claim 1 , wherein the panel comprises an insulating layer film formed between the gate electrode and the scanning lines which has a contact hole; and
one of the scanning lines is connected to the gate electrode via the contact hole provided in the interlayer insulating film.
5. The active matrix panel according to claim 4 , wherein the scanning lines formed on the insulating film and one of the first electrode and the second electrode of the gate electrode is arranged in a location which overlaps one of the scanning lines.
6. The active matrix panel according to claim 1 , wherein the second drain region of the semiconductor thin film is arranged at a location which overlaps the data lines; and
the second electrode which constitutes a segment of the data lines is formed above the second drain region.
7. The active matrix panel according to claim 1 , wherein the scanning lines are arranged closer than the bend portion of the semiconductor thin-film in the second source side; and
one of the second electrode of the gate electrode extends out to the opposite side with the second source region from the scanning lines.
8. The active matrix panel according to claim 7 , wherein the panel comprises an insulating film formed between the gate electrode and the scanning lines which has a contact hole; and
one of the scanning lines is connected to the gate electrode via the contact hole provided in the insulating film.
9. The active matrix panel according to claim 1 , wherein the panel further comprises an overcoat film formed above the switching elements; and
a pixel electrode is formed above the overcoat film.
10. The active matrix panel according to claim 1 , wherein an auxiliary capacitative electrode is formed above the gate insulating film; and
the data lines are arranged connected to the second drain region below the auxiliary capacitative electrode.
11. The active matrix panel according to claim 10 , wherein the auxiliary capacitative electrode is formed wider than the data lines.
12. The active matrix panel according to claim 1 , wherein an interlayer insulating film is formed above the gate electrodes and the gate insulating film; and
an auxiliary capacitative electrode is formed above the interlayer insulating film.
13. The active matrix panel according to claim 12 , wherein the data lines are formed below the auxiliary capacitative electrode.
14. The active matrix panel according to claim 13 , wherein the auxiliary capacitative electrode is formed wider than the data lines.
15. The active matrix panel according to claim 12 , wherein the respective scanning lines are connected to the gate electrode formed above the interlayer insulating film.
16. The active matrix panel according to claim 1 , wherein the gate insulating film and the gate electrode are formed in this order below the semiconductor thin film; and
an interlayer insulating film is formed above the semiconductor thin film.
17. The active matrix panel according to claim 16 , wherein the auxiliary capacitative electrode is formed above the interlayer insulating film.
18. The active matrix panel according to claim 17 , wherein the data lines are formed below the auxiliary capacitative electrode.
19. The active matrix panel according to claim 18 , wherein the auxiliary capacitative electrode is formed wider than the data lines.