Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.
1. A semiconductor wafer having an asymmetric edge profile (EP) extending between an inner edge profile (EP in ) and an outer edge profile (EP out ) as illustrated by FIG. 1 , which is incorporated herein;
wherein t is a thickness of the semiconductor wafer, φ 1 is an angle in a range between about 30° and about 85°, R is a radius of an arc that defines EP in at a point of intersection with a top surface of the semiconductor wafer, and α is an acute angle that represents an angle of intersection between a bottom surface of the semiconductor wafer and a line that is tangent to the arc at a point on EP out ; and
wherein:
A 1 =R (1−cos φ 1 );
A 2 =R (1−sin α)+( t−R sin φ 1 −R cos α)cot α;
B 1 =R sin φ 1 ; and
B 2 =t−R sin φ 1 .
2. The wafer of claim 1 , wherein R is in a range between about 0.23t and about 0.5t.
3. The wafer of claim 2 , wherein A 2 is greater than about two times A 1 .
4. The wafer of claim 2 , wherein φ 1 is in a range between about 60° and about 75°.
5. The wafer of claim 2 , wherein t is in a range between about 625 μm and about 825 μm.
6. A semiconductor wafer having an asymmetric edge profile (EP2) extending between an inner edge profile (EP2 in ) and an outer edge profile (EP2 out ) as illustrated by FIG. 2 , which is incorporated herein;
wherein t is a thickness of the semiconductor wafer, φ 1 is an angle in a range between about 30° and about 85°, φ 2 is greater than φ 1 and less than about 85°, R is a radius of an arc that defines EP2 in at a point of intersection with a top surface of the semiconductor wafer, and α is an acute angle that represents an angle of intersection between a bottom surface of the semiconductor wafer and a line that is tangent to the arc at a point on EP2 out ; and
wherein:
A 1 =R (1−cos φ 1 );
A 2 =R (1−sin α)+( B 2 −R cos α)cot α;
B 1 =R sin φ 1 ; and
B 2 =t−R sin φ 1 .