Isolated HF-control SCR switch

1. A vertical SCR switch capable of being controlled by a high-frequency signal, comprising at least four main layers of alternated doping types through which a large current is capable of circulating from one surface to another between two main terminals, and comprising:

a gate area connected to a gate terminal via a first integrated capacitor; and

a gate reference area connected to a gate reference terminal via a second integrated capacitors, the gate reference area being arranged on the same surface of the switch as the gate area, the gate terminal and the gate reference terminal being different from the main terminals and being adapted to receive said high-frequency signal.

2. The switch of claim 1 , of thyristor type, comprising on the front surface side a main semiconductor area of a first doping type formed in a gate semiconductor area of a second doping type, a first portion of the main area being connected to one of the main terminals, a second portion of the main area being connected to the gate reference terminal via the second integrated capacitor, and a third portion of the gate area being connected to the gate terminal via the first integrated capacitor.

3. The switch of claim 2 , wherein the first and second portions of the main area are two separate semiconductor regions.

4. The switch of claim 2 , wherein the second portion of the main area and said third portion of the gate area are each covered with an insulating layer and with a metallization, and wherein stacking of the second portion of the main area, of a first insulating portion, and of a first metallization forms the second integrated capacitor and stacking of the third portion of the gate area, of a second insulating layer, and of a second metallization forms the first integrated capacitor.

5. The switch of claim 2 , wherein the second portion of the main area is covered with a first metallization, the first metallization being connected to the gate reference terminal, and the third portion of the gate area is covered with a second metallization, the second metallization being connected to the gate terminal.

6. The switch of claim 2 , wherein the main area is a cathode area, the main area comprising one or several N-type semiconductor regions formed in a P-type well forming the gate area, the P-type well being formed above an N-type semiconductor layer under which is placed a P-type semiconductor region corresponding to a thyristor's anode.

7. The switch of claim 6 , wherein the second portion of the main area corresponding to an N-type region is placed between said first portion of the main area corresponding to an N-type region and the portion of the P-type well connected to the gate terminal.

8. The switch of claim 6 , wherein the first portion of the main area comprises several holes corresponding to portions of the P-type well, a metallization connected to a main terminal covering the first portion of the main area and all the holes.

9. The switch of claim 1 of triac type, comprising on the front surface side a main semiconductor area of a first doping type formed in a well of a second doping type, the main area and the well being connected to a main terminal, a gate region of the first doping type being formed in the well and being connected to a control terminal via a first integrated capacitor, and a portion of the well being connected to a gate reference terminal via a second integrated capacitor.

10. The switch of claim 1 of bi-directional type, comprising on the front surface side a main semiconductor area of a first doping type formed in a well of a second doping type, the main area and the well being connected to a main terminal, the assembly being surrounded with an insulating wall, a gate region of the first doping type being formed in the insulating wall or in a lateral prolongation thereof and being connected to a control terminal via a first integrated capacitor, and a portion of the well being connected to a gate reference terminal via a second integrated capacitor.

11. A thyristor being controlled by a high-frequency signal, comprising at least four main layers of alternated doping types through which a large current is capable of circulating from one surface to another between two main terminals, and comprising:

a first integrated capacitor that couples a first gate terminal to a gate area of the thyristor; and

a second integrated capacitor that couples a second gate terminal to a cathode area of the thyristor, wherein the cathode area being arranged on the same surface of the thyristor as the gate area and the first gate terminal and the second gate terminal being different from the main terminals and being adapted to receive the high-frequency signal.

12. The thyristor of claim 11 , wherein the first integrated capacitor is formed by stacking the gate area, a first insulating layer, and a first metallization, and the second integrated capacitor is formed by stacking the cathode area, a second insulating layer, and a second metallization.

13. The thyristor of claim 12 , wherein the first gate terminal is connected to the first metallization and the second gate terminal is connected to the second metallization.

14. The thyristor of claim 12 , wherein the gate area is covered by the first metallization and the cathode area is covered by the first metallization.

15. A thyristor being controlled by a high-frequency signal, comprising at least four main layers of alternated doping types through which a large current is capable of circulating from one surface to another between two main terminals, and comprising:

a first gate terminal capacitively coupled to a gate area of the thyristor via a first integrated capacitor; and

a second gate terminal capacitively coupled to a cathode area of the thyristor via a second integrated capacitor.

16. The thyristor of claim 15 , wherein the first integrated capacitor is formed by stacking the gate area, a first insulating layer, and a first metallization, and the second integrated capacitor is formed by stacking the cathode area, a second insulating layer, and a second metallization.

17. The thyristor of claim 16 , wherein the first gate terminal is connected to the first metallization and the second gate terminal is connected to the second metallization.

18. The thyristor of claim 16 , wherein the gate area is covered by the first metallization and the cathode area is covered by the first metallization.