Finfets having first and second gates of different resistivities

1. A semiconductor device comprising:

a semiconductor fin having a capping pattern thereon and protruding away from a substrate;

a first gate having a vertical part on opposite sidewalls of the capping pattern and the semiconductor fin and a horizontal part extending horizontally from the vertical part that is on the opposite sidewalls of the capping pattern, away from the semiconductor fin;

a second gate having a lower resistivity than the first gate and disposed on the vertical part of the first gate and on the capping pattern; and

a gate insulation layer disposed between the vertical part of the first gate and the semiconductor fin.

2. The semiconductor device as recited in claim 1 , wherein the first gate comprises doped polysilicon.

3. The semiconductor device as recited in claim 2 , wherein the second gate comprises metal, metallic silicide or metallic silicide and metal stacked.

4. The semiconductor device as recited in claim 3 , wherein the capping pattern comprises oxide, nitride or oxide and nitride stacked and is relatively thicker than the gate insulation layer.

5. A semiconductor device comprising:

a semiconductor fin having a capping pattern thereon and protruding away from a substrate;

a first gate having a vertical part on opposite sidewalls of the capping pattern and the semiconductor fin and a horizontal part extending horizontally from the vertical part away from the semiconductor fin;

a second gate having a lower resistivity than the first gate and disposed on the vertical part of the first gate and on the capping pattern;

a gate insulation layer disposed between the vertical part of the first gate and the semiconductor fin;

a lower insulation layer surrounding a bottom of the semiconductor fin; and

an upper insulation layer surrounding the vertical part of the first gate while being spaced apart from the semiconductor fin and being in contact with a lower surface of the horizontal part of the first gate,

wherein an upper surface of the upper insulation layer is planar.

6. The semiconductor device as recited in claim 5 , wherein the lower insulation layer comprises oxide and nitride stacked or first oxide, second oxide, and nitride stacked, and the upper insulation layer comprises oxide, the second oxide being thinner than the first oxide and the nitride being thicker than the second oxide.

7. The semiconductor device as recited in claim 5 , wherein the lower insulation layer comprises nitride or oxide and nitride stacked, and the upper insulation layer comprises oxide.

8. The semiconductor device as recited in claim 5 , wherein the capping pattern comprises oxide, nitride or oxide and nitride stacked and is thicker than the gate insulation layer.

9. A semiconductor device comprising:

a semiconductor fin having a capping pattern thereon and protruding away from a substrate;

a first gate having a vertical part on opposite sidewalls of the capping pattern and the semiconductor fin and a horizontal part extending horizontally from the vertical part away from the semiconductor fin;

a second gate having a lower resistivity than the first gate and disposed on the vertical part of the first gate and on the capping pattern;

a gate insulation layer disposed between the vertical part of the first gate and the semiconductor fin;

a buried oxide layer disposed between the substrate and the semiconductor fin;

a nitride layer disposed on the buried oxide layer to cover the bottom of the semiconductor fin; and

an oxide layer filling a space defined by a sidewall of the vertical part of the first gate, a lower side of the horizontal part of the first gate, and the nitride layer,

wherein the semiconductor fin is insulated from the substrate by the buried oxide layer.

10. The semiconductor device as recited in claim 9 , wherein the capping pattern comprises oxide, nitride or oxide and nitride stacked and is thicker than the gate insulation layer.

11. A semiconductor device comprising:

a semiconductor fin having a capping pattern thereon and protruding away from a substrate;

a first gate having a vertical part on opposite sidewalls of the capping pattern and the semiconductor fin and a horizontal part extending horizontally from the vertical part away from the semiconductor fin;

a second gate having a lower resistivity than the first gate and disposed on the vertical part of the first gate and on the capping pattern; and

a gate insulation layer disposed between the vertical part of the first gate and the semiconductor fin;

wherein a top of the vertical part of the first gate and a top of the horizontal part of the first gate have same or lower height as a top of the capping pattern, and have same or higher height as the top of the semiconductor fin.

12. A semiconductor device comprising:

a semiconductor fin having a capping pattern thereon and protruding away from a substrate;

a first gate covering opposite sidewalls of the capping pattern and the semiconductor fin with a gate insulation layer interposed therebetween; and

a second gate having a lower resistivity than the first gate and disposed directly on the first gate and directly on the capping pattern.

13. The semiconductor device as recited in claim 12 , wherein the first gate comprises polysilicon, and the second gate comprises metal of low resistivity, silicide or metal and silicide stacked.

14. The semiconductor device as recited in claim 12 , wherein the first gate comprises a vertical part on opposite sidewalls of the capping pattern and the semiconductor fin and a horizontal part extending horizontally from the vertical part, wherein the second gate is disposed directly on the horizontal part.

15. The semiconductor device as recited in claim 12 , wherein the second gate comprises silicide and metal on the silicide, wherein the silicide is disposed directly on the first gate and directly on the capping layer.