Apparatus and method for improved triggering and leakage current control of ESD clamping devices

1. An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event, comprising:

a multiple stage triggering network configured between a pair of power rails; and

a power clamp coupled to said multiple stage triggering network, said power clamp configured to discharge current from the ESD event;

said multiple stage triggering network having a first control path and a second control path configured to individually control activation of said power clamp; said first control path further comprising a first inverter coupled to a first RC trigger stage, a second inverter coupled to an output of said first inverter, and PFET switch having a gate thereof coupled to an output of said second inverter, said PFET switch further coupled to a gate of said power clamp; and

said second control path further comprising a second RC trigger stage coupled to said output of said first inverter, a third inverter coupled to said second RC trigger stage, a third RC trigger stage coupled to an output of said third inverter, and an NFET switch having a gate thereof coupled to said third RC trigger stage, said NFET switch further coupled to said gate of said power clamp.

2. The apparatus of claim 1 , wherein said power clamp further comprises an NFET.

3. The apparatus of claim 1 , wherein a resistive component of said first RC trigger stage is implemented by a diode configured PFET.

4. The apparatus of claim 3 , wherein a resistive component of said second RC trigger stage is implemented by a PFET having a gate terminal connected to said output of said first inverter.

5. The apparatus of claim 4 , wherein a resistive component of said third RC trigger stage is implemented by a PFET having a gate terminal connected to said output of said third inverter.

6. The apparatus of claim 1 , wherein a total time delay of said first, second and third RC trigger stages corresponds to a first value for non-ESD power-up events, and corresponds to a second value for an ESD event.

7. The apparatus of claim 1 , wherein, during an ESD event, said multiple stage triggering network is configured to allow the voltage on said gate of said power clamp to float after a period of time corresponding to a time constant of said first RC trigger stage.

8. The apparatus of claim 6 , wherein, during a power up operation of the integrated circuit, said total time delay is about 150 ns or less, and during an ESD event said total time delay is at least about 1 μs.

9. A method for protecting an integrated circuit from an electrostatic discharge (ESD) event, comprising:

configuring a multiple stage triggering network between a pair of power rails; and

coupling a power clamp to said multiple stage triggering network, said power clamp configured to discharge current from the ESD event;

said multiple stage triggering network having a first control path and a second control path configured to individually control activation of said power clamp; said first control path further comprising a first inverter coupled to a first RC trigger stage, a second inverter coupled to an output of said first inverter, and PFET switch having a gate thereof coupled to an output of said second inverter, said PFET switch further coupled to a gate of said power clamp; and

said second control path further comprising a second RC trigger stage coupled to said output of said first inverter, a third inverter coupled to said second RC trigger stage, a third RC trigger stage coupled to an output of said third inverter, and an NFET switch having a gate thereof coupled to said third RC trigger stage, said NFET switch further coupled to said gate of said power clamp.

10. The method of claim 9 , wherein said power clamp further comprises an NFET.

11. The method of claim 9 , wherein a resistive component of said first RC trigger stage is implemented by a diode configured PFET.

12. The method of claim 11 , wherein a resistive component of said second RC trigger stage is implemented by a PFET having a gate terminal connected to said output of said first inverter.

13. The method of claim 12 , wherein a resistive component of said third RC trigger stage is implemented by a PFET having a gate terminal connected to said output of said third inverter.

14. The method of claim 9 , wherein a total time delay of said first, second and third RC trigger stages corresponds to a first value for non-ESD power-up events, and corresponds to a second value for an ESD event.

15. The method of claim 9 , wherein, during an ESD event, said multiple stage triggering network is configured to allow the voltage on said gate of said power clamp to float after a period of time corresponding to a time constant of said first RC trigger stage.

16. The method of claim 14 , wherein, during a power up operation of the integrated circuit, said total time delay is about 150 ns or less, and during an ESD event said total time delay is at least about 1 μs.