Logically grouping physical ports into logical interfaces to expand bandwidth
View Patent ↗A method, system and computer program product for routing packets. A network device, e.g., router, may comprise a switch fabric coupled to a plurality of blades where each blade may comprise one or more network processors coupled to one or more physical ports. The physical ports may be connected to another one or more network devices. A plurality of physical ports across one or more blades connected to the same network device may be logically mapped into a logical interface to that network device. By logically grouping a plurality of physical ports into a logical interface to a network device, a network processor may be able to transmit packets of data to that network device across multiple ports instead of one physical port.
1. A method for routing packets comprising the steps of:
mapping a plurality of physical ports into a logical interface to a network device, wherein said plurality of physical ports are connected to one or more processors, wherein said one or more processors are configured to process packets of data;
receiving a packet of data;
transmitting said received packet of data to one of said plurality of physical ports of said logical interface; and
indexing a first table to determine a second table associated with said logical interface.
2. The method as recited in claim 1 , wherein said first table is indexed using a destination address of said received packet.
3. The method as recited in claim 1 further comprising the steps of:
performing a hash function on said received packet to generate a hash value;
indexing into said second table using said generated hash value; and
identifying one of said plurality of ports to transmit said received packet from said second table using said generated hash value.
4. The method as recited in claim 3 , wherein a blade is identified from said second table using said generated hash value.
5. The method as recited in claim 3 , wherein said hash function is performed on a source address and a destination address of said received packet to generate said hash value.
6. A computer program product embodied in a machine readable medium for routing packets comprising the programming steps of:
mapping a plurality of physical ports into a logical interface to a network device, wherein said plurality of physical ports are connected to one or more processors, wherein said one or more processors are configured to process packets of data
receiving a packet of data;
transmitting said received packet of data to one of said plurality of physical ports of said logical interface; and
indexing a first table to determine a second table associated with said logical interface.
7. The computer program product as recited in claim 6 , wherein said first table is indexed using a destination address of said received packet.
8. The computer program product as recited in claim 6 further comprising the programming steps of:
performing a hash function on said received packet to generate a hash value;
indexing into said second table using said generated hash value; and
identifying one of said plurality of ports to transmit said received packet from said second table using said generated hash value.
9. The computer program product as recited in claim 8 , wherein a blade is identified from said second table using said generated hash value.
10. The computer program product as recited in claim 8 , wherein said hash function is performed on a source address and a destination address of said received packet to generate said hash value.
11. A network processor, comprising:
a memory unit operable for storing a computer program operable for routing packets; and
processor coupled to said memory unit, wherein said processor, responsive to said computer program, comprises:
circuitry operable for mapping a plurality of physical ports into a logical interface to a network device, wherein said plurality of physical ports are connected to one or more network processors, wherein said one or more network processors are configured to process packets of data;
circuitry operable for receiving a packet of data;
circuitry operable for transmitting said received packet of data to one of said plurality of physical ports of said logical interface; and
circuitry operable for indexing a first table to determine a second table associated with said logical interface.
12. The system as recited in claim 11 , wherein said first table is indexed using a destination address of said received packet.
13. The system as recited in claim 11 , wherein said processor further comprises:
circuitry operable for performing a hash function on said received packet to generate a hash value;
circuitry operable for indexing into said second table using said generated hash value; and
circuitry operable for identifying one of said plurality of ports to transmit said received packet from said second table using said generated hash value.
14. The system as recited in claim 13 , wherein a blade is identified from said second table using said generated hash value.
15. The system as recited in claim 13 , wherein said hash function is performed on a source address and a destination address of said received packet to generate said hash value.
16. A system, comprising:
a plurality of blades; and
a switch fabric coupled to said plurality of blades, wherein said switch fabric is configured to direct incoming packets of data to particular blades;
wherein each of said plurality of blades comprises:
a first processor, wherein said first processor is configured to process packets of data; and
one or more ports coupled to said first processor, wherein said one or more ports are configured to transmit processed packets of data;
wherein said first processor comprises:
a memory unit operable for storing a computer program operable for routing packets; and
a second processor coupled to said memory unit, wherein said second processor, responsive to said computer program, comprises:
circuitry operable for mapping a plurality of ports of one or more blades into a logical interface to a network device;
circuitry operable for receiving a packet of data;
circuitry operable for transmitting said received packet of data to one of said plurality of physical ports of said logical interface; and
circuitry operable for indexing a first table to determine a second table associated with said logical interface.
17. The system as recited in claim 16 , wherein said first table is indexed using a destination address of said received packet.
18. The system as recited in claim 16 , wherein said second processor further comprises:
circuitry operable for performing a hash function on said received packet to generate a hash value;
circuitry operable for indexing into said second table using said generated hash value; and
circuitry operable for identifying one of said plurality of ports to transmit said received packet from said second table using said generated hash value.
19. The system as recited in claim 18 , wherein a blade is identified from said second table using said generated hash value.
20. The system as recited in claim 18 , wherein said hash function is performed on a source address and a destination address of said received packet to generate said hash value.