Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip
A microelectronic device chip including a hybrid Au bump in which foreign materials are not generated in a probe tip in an electrical die sorting (EDS) test is provided. The microelectronic device chip includes a chip pad which is connected to a microelectronic device formed on a substrate and on which the microelectronic device is brought into electrical contact with the outside of the chip. Further, the microelectronic device chip includes a bump which is formed on the chip pad and made up of a composite layer including two or more layers.
1. A microelectronic device chip comprising:
a chip pad which is connected to a microelectronic device formed on a substrate to bring the microelectronic device into electrical contact with the outside of the chip; and
a hybrid Au bump which is formed on the chip pad and in which a cyan Au plating layer and a non-cyan Au plating layer are stacked.
2. The microelectronic device chip of claim 1 , wherein the hybrid Au bump has a thickness in the range of 1-20 μm.
3. The microelectronic device chip of claim 2 , wherein thicknesses of the cyan Au plating layer and the non-cyan Au plating layer are not less than 0.5 μm.
4. The microelectronic device chip of claim 3 , wherein the cyan Au plating layer of the hybrid Au bump is located on the chip pad and the non-cyan Au plating layer of the hybrid Au bump is located on the cyan Au plating layer.
5. The microelectronic device chip of claim 3 , wherein the non-cyan Au plating layer of the hybrid Au bump is located on the chip pad and the cyan Au plating layer of the hybrid Au bump is located on the non-cyan Au plating layer.
6. A microelectronic device chip comprising:
a chip pad which is connected to a microelectronic device formed on a substrate to bring the microelectronic device into electrical contact with the outside of the chip;
a passivation layer which protects the microelectronic device and exposes the chip pad;
a hybrid Au bump which is formed on the chip pad exposed by the passivation layer and in which a cyan Au plating layer and a non-cyan Au plating layer are stacked; and
a bump lower conductive layer which is formed between the chip pad and the bump to prevent mutual diffusion between the chip pad and the bump, and improve adhesion between the chip pad and the bump.
7. The microelectronic device chip of claim 6 , wherein the hybrid Au bump has a thickness in the range of 1-20 μm.
8. The microelectronic device chip of claim 7 , wherein thicknesses of the cyan Au plating layer and the non-cyan Au plating layer are not less than 0.5 μm.
9. The microelectronic device chip of claim 8 , wherein the cyan Au plating layer of the hybrid Au bump is located on the chip pad and the non-cyan Au plating layer of the hybrid Au bump is located on the cyan Au plating layer.
10. The microelectronic device chip of claim 8 , wherein the cyan Au plating layer of the hybrid Au bump is located on the chip pad and the cyan Au plating layer of the hybrid Au bump is located on the non-cyan Au plating layer.
11. The microelectronic device chip of claim 7 , wherein the bump lower conductive layer is formed of at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au and Ni V/Cu.
12. The microelectronic device chip of claim 11 , wherein the bump lower conductive layer has a stacked structure comprising 0.005-0.5 μm thick TiW and 0.005-0.5 μm thick Au.
13. The microelectronic device chip of claim 6 , wherein the hybrid Au bump has a structure in which one or more cyan Au plating layers and one or more non-cyan Au plating layers are stacked alternately.
14. A package comprising a microelectronic device chip according to any one of claims 1 , 2 - 6 and 7 - 13 and a tape wiring board which includes wirings made up of external connection terminals and internal connection terminals electrically connected to a bump of the microelectronic device chip.
15. A liquid crystal display apparatus comprising a microelectronic device chip according to any one of claims 1 , 2 - 6 and 7 - 13 and a liquid crystal display panel assembly in which wirings for connecting to the microelectronic device chip are formed; wherein a bump of the microelectronic device chip is electrically connected to the wirings.
16. The liquid crystal display apparatus of claim 15 , wherein the microelectronic device chip is connected to the liquid crystal display panel assembly using one of a chip-on-glass (COG) method, a tape carrier package (TCP) method and a chip-on-film (COF) method.