Self correcting suppression of threshold voltage variation in fully depleted transistors
View Patent ↗A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.
1. A semiconductor fabrication method, comprising:
introducing a counter doping impurity distribution having a first conductivity type into a semiconductor layer of a semiconductor-on-insulator (SOI) wafer having a second conductivity type, the SOI wafer including the semiconductor layer overlying a buried oxide (BOX) layer;
wherein the top semiconductor layer has a first thickness at a first region in the wafer and a second thickness at a second region in the wafer wherein the first thickness is less than the second thickness;
wherein the counter doping impurity distribution is introduced wherein a first percentage of the impurity distribution is located in the semiconductor layer at the first region and wherein a second percentage of the impurity does is located in the semiconductor layer at the second region, wherein the first percentage is less than the first;
wherein the counter doping impurity distribution reduces a difference in net charge between the first region and the second region.
2. The method of claim 1 , further comprising forming a first fully depleted transistor overlying the first region and a second fully depleted transistor overlying the second region, wherein a depletion region in a channel of the first and second transistors extends from an upper surface of the semiconductor layer to the BOX layer.
3. The method of claim 1 , wherein introducing the counter doping impurity distribution comprises ion implanting the counter doping impurity distribution into the semiconductor layer.
4. The method of claim 3 , wherein the second thickness of the semiconductor layer is a maximum thickness (T MAX ) of the semiconductor layer and further wherein implanting the counter doping impurity distribution comprises implanting the counter doping impurity distribution wherein a depth of a peak concentration of the implanted impurity distribution is greater than the maximum thickness.
5. The method of claim 4 , wherein implanting the impurity distribution includes implanting the impurity distribution with a projected range (R P ) wherein R P /T MAX is in the range of approximately 1.08 to 1.20.
6. The method of claim 5 , wherein implanting the impurity distribution includes implanting the impurity distribution with a projected straggle (ΔR P ), wherein ΔR P /R P is in the range of approximately 0.2 to 0.3.
7. The method of claim 1 , further comprising, prior to introducing the impurity distribution into the semiconductor layer, forming a sacrificial layer overlying the semiconductor layer.
8. A semiconductor fabrication method for use with a semiconductor-on-insulator (SOI) wafer having a semiconductor layer overlying a buried oxide (BOX) layer, comprising:
implanting a counter doping impurity distribution into the SOI wafer, wherein a peak concentration of the counter doping impurity distribution is located at a depth that is greater than a maximum thickness of the semiconductor layer; and
wherein a first percentage of the impurity distribution contributes to the net depletion charge in a first region of the semiconductor layer and wherein a second percentage of the impurity distribution contributes to the net depletion charge in a second region of the semiconductor layer wherein the first percentage and the second percentage differ.
9. The method of claim 8 , wherein the first thickness and the second thickness differ and wherein net depletion charge in the first and second regions is approximately equal when the semiconductor layer is biased to full depletion.
10. The method of claim 8 , wherein implanting the counter doping impurity distribution includes selectively implanting the a first counter doping impurity distribution into NMOS regions of the semiconductor layer and selectively implanting a second counter doping impurity distribution into PMOS regions of the semiconductor layer.
11. The method of claim 10 , wherein the first counter doping impurity distribution comprises an arsenic impurity distribution and wherein the second counter doping impurity distribution comprises a boron impurity distribution.
12. The method of claim 11 , wherein the semiconductor layer comprises silicon and has a maximum thickness of approximately 27.5 nm and an acceptor atom doping concentration (N A ) of approximately 5×10 17 cm −3 in the NMOS regions, and wherein implanting the first counter doping impurity distribution comprises implanting arsenic using a dose of approximately 1.2×10 12 cm −2 and an energy of approximately 42 keV.
13. The method of claim 8 , wherein a thickness of the semiconductor layer varies from the first region to the second region.
14. The method of claim 13 , wherein the first and second percentages vary approximately linearly with the thickness of the semiconductor layer in the first and second regions respectively.
15. The method of claim 8 , wherein the depth of the peak concentration of the counter doping impurity distribution is greater than the maximum thickness by approximately 8 to 20%.