IP Library Granted Patent US 7,291,901
Granted Patent B2
US 7,291,901 · App. 10/803,879 · Granted Nov 6, 2007

Packaging method, packaging structure and package substrate for electronic parts

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,291,901
App. No.
10/803,879
Granted
Nov 6, 2007
Kind
B2
Abstract

A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12 , a thin film substrate (a second substrate) 13 is laminated on the first substrate 12 , the opening 11 is covered with the thin film substrate 13 . Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15 , an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13 , and the capacitor 14 is connected to the LSI 16.

Claims (16)

1. A packaging structure for electronic parts comprising:

a first substrate having an opening;

a second substrate laminated on the first substrate and covering the opening;

a first electronic part inserted into the opening and bonded to the second substrate;

a hard resin filling an interior of the opening;

a second electronic part bonded to a surface, on an exposed side, of the second substrate;

wiring for connecting the first electronic part to the second electronic part; and

wherein the first substrate includes a sustaining member provided within the opening, bonded to an inner peripheral surface of the opening and sustaining an exposed surface of the resin.

2. A packaging structure for electronic parts according to claim 1 , wherein the second substrate is a thin film.

3. A packaging structure for electronic parts according to claim 1 , wherein the first electronic part is a capacitor, and the second electronic part is an LSI.

4. A packaging structure for electronic parts according to claim 1 , wherein the resin contains a filler agent.

5. A packaging structure for electronic parts according to claim 1 , wherein a coefficient of thermal expansion of the resin is adjusted according to the first and second substrates, and the first and second electronic parts.

6. A packaging structure for electronic parts according to claim 1 , wherein a fin for cooling is bonded to the second electronic part.

7. A packaging structure for electronic parts according to claim 1 , wherein the second substrate has a stiffener for reinforcement.

8. A packaging structure for electronic parts according to claim 7 , wherein the stiffener is provided on the side of the first electronic part.

9. A packaging structure for electronic parts according to claim 7 , wherein the stiffener is provided on an outer peripheral edge of the thin film substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2004
From: KOIDE, MASATERU; UMEMATSU, MISAO; KANDA, TAKASHI; USUI, YASUHIRO; FUKUZONO, KENJI
To: FUJITSU LIMITED
Reel/Frame 015120/0460 →
Priority Claims (1)
JP 2003-078354 · Mar 20, 2003 · national
Continuity (1)
Related Publication 20040183193A1 · Sep 23, 2004