Semiconductor integrated circuit device

1. A semiconductor integrated circuit device comprising:

a first input capacitor;

a second input capacitor;

a feedback capacitor composed of a variable capacitor device; and

an amplifier circuit,

wherein, at first timing, the first input capacitor acquires a first signal, and the amplifier circuit amplifies the second signal acquired to the second input capacitor according to a gain corresponding to a capacity ratio between the second input capacitor and the feedback capacitor,

wherein, at second timing, the second input capacitor acquires a second signal, and the amplifier circuit amplifies the first signal according to a gain corresponding to a capacity ratio between the first input capacitor and the feedback capacitor, and

wherein a variable gain amplifier circuit interleavingly amplifies the first signal and the second signal in accordance with the first timing and the second timing.

2. The semiconductor integrated circuit device according to claim 1 ,

wherein the feedback capacitor is capable of variable capacitance values since a switch device selectively connects a plurality of capacitor devices in a parallel mode.

3. The semiconductor integrated circuit device according to claim 2 ,

wherein the amplifier circuit is provided with differential input and differential output,

wherein the first and second input capacitors include two pairs of capacitors corresponding to differential input, and

wherein the feedback capacitor includes two pairs of variable capacitors corresponding to the differential input and output.

4. The semiconductor integrated circuit device according to claim 3 ,

wherein the first timing and the second timing have timing to reset the feedback capacitor before the amplifier circuit starts amplification or after the amplifier circuit completes amplification.

5. The semiconductor integrated circuit device according to claim 4 ,

wherein a switch comprised of MOSFET is used for switching between acquiring and amplifying an input signal to first and second input capacitors at the first and second timings and between an amplification operation and a reset operation using the feedback capacitor, and

wherein a MOSFET to reset the feedback capacitor is sized large enough to have an on-resistance value smaller than that for MOSFET used for the other switches.

6. The semiconductor integrated circuit device according to claim 4 ,

wherein the amplifier circuit constructs a correlated double sampling circuit that samples and holds a signal corresponding to a black level of a feed-through portion of a pixel signal generated in a solid-state image sensor and generates an output signal corresponding to a difference signal between the feed-through portion and a signal portion of the pixel signal,

wherein the first timing includes a first period and the second timing includes a second period,

wherein the first signal corresponds to a black level of the feed-through portion in the first period and a level of a signal portion for the pixel signal immediately after the first period, and

wherein the second signal corresponds to a black level of the feed-through portion in the second period and a level of a signal portion for the pixel signal immediately after the second period.

7. The semiconductor integrated circuit device according to claim 6 further comprising:

a variable amplifier circuit,

wherein the amplifier circuit of the variable amplifier circuit receives a differential signal of the correlated double sampling circuit, and

wherein the first and second signals input to the variable amplifier circuit are pixel signals chronologically output from the correlated double sampling circuit.

8. The semiconductor integrated circuit device according to claim 7 further comprising:

an A/D converter circuit;

a logical circuit that receives an output signal from the A/D converter circuit and feeds back a black level clamp signal to the correlated double sampling circuit; and

a voltage holding circuit that holds the black level clamp signal,

wherein the A/D converter circuit includes a sample/hold circuit that performs an interleave operation synchronized with an amplification output operation of the variable amplifier circuit.

9. The semiconductor integrated circuit device according to claim 8 ,

wherein a black level clamp signal generated in the voltage holding circuit is supplied to reference voltage sides of the first and second input capacitors of the amplifier circuit constituting the correlated double sampling circuit.

10. The semiconductor integrated circuit device according to claim 9 ,

wherein the black level clamp signal is fed back as reverse polarities to input capacitors corresponding to a positive input terminal and a negative input terminal of the amplifier circuit.

11. The semiconductor integrated circuit device according to claim 7 ,

wherein an offset adjustment voltage is synchronized with acquisition timings of the first and second signals and is acquired to the first and second input capacitors of the amplifier circuit constituting the variable amplifier circuit, and

wherein the semiconductor integrated circuit device further comprises first and second offset adjustment capacitors that are parallel connected to the first and second input capacitors correspondingly to the amplification operation.