Clock circuitry for programmable logic devices
Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.
1. Data transmitter circuitry on a PLD comprising:
a plurality of channels of data serializer circuitry, each of which is configured to receive data in parallel and convert that data to serial form for transmission;
a plurality of physical coding sublayer (“PCS”) channels, each of which is associated with a respective one of the serializer channels for supplying parallel data to the associated serializer channel when triggered by a clock signal; and
circuitry associated with each of the PCS channels for selecting the clock signal for that PCS channel from a local clock signal and a global clock signal that can be common to as many as eight of the serializer channels.
2. The circuitry defined in claim 1 wherein the local clock signal available to each of the PCS channels is produced by the serializer channel associated with that PCS channel.
3. The circuitry defined in claim 1 further comprising:
circuitry for selecting the global clock signal from a first clock signal that is common to up to four of the serializer channels and a second clock signal that is common to up to eight of the serializer channels.
4. The circuitry defined in claim 1 further comprising:
a plurality of clock multiplier unit (“CMU”) circuitries, each of which is associated with a respective subplurality of the serializer channels;
circuitry for supplying a plurality of clock signals from each of the CMUs to the serializer channels associated with that CMU; and
local clock generation and buffering (“CGB”) circuitry associated with each of the serializer channels for possible use to produce the local clock signal for the associated PCS channel based on a clock signal from the associated CMU.
5. The circuitry defined in claim 4 wherein each of the CMUs comprises:
central CGB circuitry for possible use to produce the global clock signal.
6. The circuitry defined in claim 5 wherein the circuitry for supplying supplies both clock signals from the CMU that have not been processed by the CGB of the CMU and clock signals from the CMU that have been processed by the CGB of the CMU.
7. The circuitry defined in claim 6 wherein each of the serializer channels comprises:
selection circuitry for selecting for use by that serializer channel either clock signals from a CMU that have not been processed by the CGB of a CMU or clock signals from a CMU that have been processed by the CGB of a CMU.
8. The circuitry defined in claim 7 wherein each serializer channel comprises:
circuitry for applying clock signals from a CMU that have not been processed by the CGB of a CMU to the local CGB circuitry of the serializer channel.
9. Data transmitter circuitry on a PLD comprising:
a plurality of data serializer channels;
a plurality of clock multiplier units (“CMUs”) each of which is associated with a respective subplurality of the serializer channels, and each of which produces a raw clock signal and a centrally processed clock signal;
distribution circuitry for distributing the raw clock signal of each CMU to the serializer channels associated with that CMU, and for distributing the centrally processed clock signal of each CMU to the serializer channels associated with that CMU and another of the CMUs;
circuitry associated with each of the serializer channels for selecting any of the clock signals the distribution circuitry distributes to that channel for use by that channel;
a physical coding sublayer (“PCS”) channel associated with each of the serializer channels for releasing parallel data to the associated serializer channel in response to a PCLK signal; and
circuitry for selecting the PCLK signal for use by each of the PCS channels from either a clock signal output by the serializer channel associated with that PCS channel or a centrally processed clock signal produced by either of two of the CMUs.
10. Data transmitter circuitry on a PLD comprising:
a plurality of data serializer channels;
a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels, and each of which produces a raw clock signal and a centrally processed clock signal;
distribution circuitry for distributing the raw clock signal of each CMU to the serializer channels associated with that CMU, and for distributing the centrally processed clock signal of each CMU to the serializer channels associated with that CMU and another of the CMUs;
a physical coding sublayer (“PCS”) channel associated with each of the serializer channels for releasing parallel data to the associated serializer channel in response to a PCLK signal; and
circuitry for selecting the PCLK signal for use by each of the PCS channels from a signal output by the serializer channel associated with that PCS channel or a signal output by any CMU from which a signal is distributed to that serializer channel.
11. The circuitry defined in claim 10 wherein the signal output by each serializer channel is derived from the raw clock signal distributed to that serializer channel.
12. The circuitry defined in claim 10 wherein the signal output each CMU is derived from the centrally processed clock signal of that CMU.
13. The circuitry defined in claim 10 wherein each PCS channel includes:
circuitry for selecting the PCLK signal to be used by that channel from the output signal of the serializer channel associated with that PCS channel and a PCLK output signal of the CMU associated with that serializer channel.
14. The circuitry defined in claim 13 wherein each CMU comprises:
circuitry for selecting the PCLK output signal of that CMU from a signal derived from the centrally processed clock signal of that CMU and the PCLK output signal of another CMU.
15. The circuitry defined in claim 10 wherein each of the serializer channels comprises:
local clock generation and buffering (“CGB”) circuitry for processing a raw clock signal distributed to that serializer channel.
16. The circuitry defined in claim 10 wherein each CMU comprises:
central CGB circuitry for producing the centrally processed clock signal.
17. The circuitry defined in claim 10 wherein each CMU comprises:
a plurality of reference clock signal sources;
a plurality of phase-locked loop (“PLL”) circuits; and
circuitry for applying any of the reference clock signals to any of the PLL circuits.
18. The circuitry defined in claim 17 wherein the raw clock signal produced by each CMU is derived from a first one of the PLL circuits of that CMU, and wherein the centrally processed clock signal produced by each CMU is derived from a second one of the PLL circuits of that CMU.
19. The circuitry defined in claim 15 wherein the local CGB circuitry produces both relatively high and relatively low frequency clock signals based on the raw clock signal.
20. The circuitry defined in claim 16 wherein the central CGB circuitry produces a plurality of centrally processed signals, including both relatively high and relatively low frequency signals.
21. The circuitry defined in claim 20 wherein the distribution circuitry distributes the plurality of centrally processed signals of each CMU to the serializer channels associated with that CMU and another of the CMUs.