System, method and storage medium for bus calibration in a memory subsystem
View Patent ↗A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.
1. A cascaded interconnect system comprising:
one or more memory modules;
a memory controller; and
a memory bus that utilizes periodic recalibration, wherein the memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration, and wherein the memory bus includes an upstream memory bus with twenty-three wires and the periodic calibration is performed for each of the wires.
2. The system of claim 1 further comprising a sampling clock, wherein the recalibration includes synchronizing the sampling clock and a data phase of the scrambled data for data sampling on the memory bus.
3. The system of claim 1 further comprising a sampling clock wherein the recalibration includes adjusting the sampling clock so that it is centered between two consecutive edges of data on the memory bus.
4. The system of claim 1 wherein the memory bus includes a segment providing a connection between one of the memory modules and the memory controller or between two of the memory modules, the segment including a transmit side where scrambling is performed on input data resulting in scrambled data and a receive side where de-scrambling is performed on the scrambled data resulting in the input data.
5. The system of claim 4 further comprising circuitry for performing the scrambling and the de-scrambling.
6. The system of claim 4 wherein the scrambling and the de-scrambling are synchronized between the transmit side and the receive side.
7. The system of claim 4 wherein input to the scrambling and the de-scrambling includes a scrambling pattern.
8. The system of claim 4 wherein the scrambling and the de-scrambling are synchronized at system initialization.
9. The system of claim 4 wherein the scrambling and the de-scrambling are synchronized periodically during system operation.
10. The system of claim 1 wherein the memory modules operate at a memory module data rate and the memory bus operates at four times the memory module data rate.
11. The system of claim 1 wherein the memory bus includes an upstream memory bus and a downstream memory bus.
12. A method for providing bus recalibration, the method comprising:
receiving input data at a transmit side, the transmit side including a memory controller or a memory module within a cascaded interconnect memory system;
scrambling the input data at the transmit side resulting in scrambled data;
transmitting the scrambled data to a receive side via a memory bus, the receive side including an other memory controller or memory module within the memory system, and the receive side directly connected to the transmit side by a packetized multi-transfer interface via the memory bus;
periodically synchronizing a sampling clock and a data phase of the scrambled data at the receive side for data sampling on the memory bus; and
de-scrambling the scrambled data at the receive side resulting in the input data, wherein the memory bus includes a downstream memory bus with twenty-two wires and the periodic synchronizing is performed for each of the wires.
13. The method of claim 12 wherein the synchronizing includes determining a phase of the sampling clock for the data sampling on the memory bus.
14. The method of claim 12 wherein the synchronizing includes adjusting a phase of the sampling clock so that it is centered between two consecutive edges of the scrambled data on the memory bus.
15. The method of claim 12 wherein the scrambling and the de-scrambling are synchronized between the transmit side and the receive side.
16. The method of claim 12 wherein input to the scrambling and the de-scrambling includes a scrambling pattern.
17. The method of claim 12 wherein the scrambling and the de-scrambling are synchronized at system initialization.
18. The method of claim 12 wherein the scrambling and the de-scrambling are synchronized periodically during system operation.
19. The method of claim 12 wherein the memory modules operate at a memory module data rate and the memory bus operates at four times the memory module data rate.
20. The method of claim 12 wherein the memory bus includes an upstream memory bus and a downstream memory bus.
21. A cascaded interconnect system comprising:
one or more memory modules;
a memory controller; and
a memory bus that utilizes periodic recalibration, wherein the memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration, and wherein the memory bus includes a downstream memory bus with twenty-two wires and the periodic calibration is performed for each of the wires.
22. A method for providing bus recalibration, the method comprising:
receiving input data at a transmit side, the transmit side including a memory controller or a memory module within a cascaded interconnect memory system;
scrambling the input data at the transmit side resulting in scrambled data;
transmitting the scrambled data to a receive side via a memory bus, the receive side including an other memory controller or memory module within the memory system, and the receive side directly connected to the transmit side by a packetized multi-transfer interface via the memory bus;
periodically synchronizing a sampling clock and a data phase of the scrambled data at the receive side for data sampling on the memory bus; and
de-scrambling the scrambled data at the receive side resulting in the input data, wherein the memory bus includes an upstream memory bus with twenty-three wires and the periodic synchronizing is performed for each of the wires.