Processor-based structure and method for loading unaligned data
A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.
1. A processor-based method for loading unaligned data, wherein the unaligned data is divided by word boundaries into a first part, a second part and a third part, and stored in a memory having a plurality of m (positive integer)-bit words partitioned by word boundaries, the method comprising:
a first fetching step, which executes a first instruction to fetch a first word from the memory having the first part;
a second fetching step, which executes a second instruction to fetch a second word from the memory having the second part;
a first shifting step, which combines the first word and the second word to form a first combination and shifts the first combination to a first position;
a third fetching step, which executes a third instruction to fetch a third word from the memory having the third part; and
a second shifting step, which combines the second word and the third word to form a second combination and shifts the second combination to the first position.
2. The method as claimed in claim 1 , further comprising:
a repeat fetching step, which replaces the second word with the first word and executes a second instruction to fetch a second word from the memory having the second part; and
a third shifting step, which combines the first word and the second word to form a third combination and shifts the third combination to the first position.
3. The method as claimed in claim 1 , wherein the shifting steps perform shift.
4. The method as claimed in claim 1 , wherein the shifting steps perform rotation.
5. The method as claimed in claim 1 , wherein the first part and the third part have a size less than m bits respectively.
6. The method as claimed in claim 1 , wherein the first part has a size equal to m bits.
7. The method as claimed in claim 2 , wherein m is 32.
8. The method as claimed in claim 2 , wherein the first, the second and the third shifting steps performs shifting left by eight bits respectively.
9. The method as claimed in claim 2 , wherein the first, the second and the third shifting steps performs shifting left by 16 bits respectively.
10. The method as claimed in claim 2 , wherein the first, the second and the third shifting steps performs shifting left by 24 bits respectively.
11. A processor-based method for loading unaligned data, wherein the unaligned data is stored in a memory having a plurality of m (positive integer)-bit words partitioned by word boundaries, and divided by word boundaries into a first part and a second part, the method comprising:
a start fetching step, which executes a first instruction to fetch a first word from the memory having the first part;
an end fetching step, which executes a second instruction to fetch a second word from the memory having the second part; and
a first shifting step, which combines the first word and the second word to form a first combination and shifts the first combination to a first position.
12. The method as claimed in claim 11 , wherein the first shifting step performs shift.
13. The method as claimed in claim 11 , wherein the first shifting step performs rotation.
14. The method as claimed in claim 11 , wherein the first part and the second part have a size less than m bits respectively.
15. The method as claimed in claim 11 , wherein the first part has a size equal to m bits.
16. The method as claimed in claim 11 , wherein m is 32.
17. The method as claimed in claim 16 , wherein the first shifting step performs shifting left by eight bits.
18. The method as claimed in claim 16 , wherein the first shifting step performs shifting left by 16 bits.
19. The method as claimed in claim 16 , wherein the first shifting step performs shifting left by 24 bits.
20. A processor-based device for loading unaligned data, wherein the unaligned data is divided by word boundaries into a first part, a second part and a third part, and stored in a memory having a plurality of m (positive integer)-bit words partitioned by word boundaries, the device comprising:
a load combine register, which is coupled to the memory for temporarily storing data read out of the memory;
a shifter, which is coupled to the load combine register and the memory for shifting in accordance with stored address of the unaligned data; and
a controller, which firstly fetches a first word from the memory having the first part for storing in the load combine register temporarily, then fetches a second word from the memory having the second part such that the shifter combines the first word and the second word to form a first combination and shifts the first combination to a first position, and finally fetches a third word from the memory having the third part such that the shifter combines the second word and the third word to form a second combination and shifts the second combination to the first position.
21. The device as claimed in claim 20 , wherein the shifter applies shift to the load combine register and the memory.
22. The device as claimed in claim 20 , wherein the shifter applies rotation to the load combine register and the memory.
23. The device as claimed in claim 20 , wherein the first part and the third part have a size less than m bits respectively.
24. The device as claimed in claim 20 , wherein the first part has a size equal to m bits.
25. The device as claimed in claim 20 , wherein m is 32.
26. The device as claimed in claim 20 , wherein the shifter performs shifting left by eight bits.
27. The device as claimed in claim 20 , wherein the shifter performs shifting left by 16 bits.
28. The device as claimed in claim 20 , wherein the shifter performs shifting left by 24 bits.