Flash memory device
A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.
1. A flash memory device comprising:
a first selection transistor coupled to a bitline;
a second selection transistor coupled to a common source line;
a plurality of memory cells coupled between the first and second selection transistors, each memory cell being coupled to a wordline, and
a single dummy memory cell provided between the first selection transistor and one of the memory cells which is adjacent to the first selection transistor or between the second selection transistor and one of the memory cells which is adjacent to the second selection transistor,
wherein the dummy memory cell is supplied with a program inhibit voltage applied to the dummy memory cell during a program operation.
2. The flash memory device of claim 1 , wherein the memory cell which is adjacent to the first selection transistor and a deselected bitline of the bitlines are substantially free from an effect of program disturbance.
3. The flash memory as set forth in claim 1 , wherein the dummy memory cell is supplied with a voltage that is more than twice a power source voltage and less than a program inhibit voltage during a program operation.
4. The flash memory as set forth in claim 1 , wherein the dummy memory cell is supplied with a ground voltage during an erase operation and supplied with a read voltage applied to the dummy memory cell during a read operation.
5. The flash memory as set forth in claim 1 , wherein the dummy memory cell has the same size as the plurality of memory cells coupled between the first and second selection transistors.
6. The flash memory as set forth in claim 1 , wherein each of the memory cells is configured to store at least two bits of data, the dummy memory cell not being configured to store at least two bits of data.
7. A flash memory device comprising:
a first selection transistor coupled to a bitline;
a second selection transistor coupled to a common source line;
a plurality of memory cells provided between the first and second selection transistors, each memory cell being coupled to a wordline; and
a single dummy transistor provided between the first selection transistor and one of the memory cells which is adjacent to the first selection transistor or between the second selection transistor and one of the memory cells which is adjacent to the second selection transistor, wherein a dummy transistor is conditioned in a floating state during an erase operation.
8. The flash memory as set forth in claim 7 , wherein threshold voltages of memory cells adjacent to the first selection or the second selection transistor and a selected bitline of the plurality of bitlines are equal to threshold voltages of the other memory cells.
9. The flash memory as set forth in claim 7 , wherein a dummy transistor is supplied with a power source voltage during program and read operations.
10. The flash memory as set forth in claim 7 , wherein the memory cells including the dummy transistor have substantially the same size.
11. The flash memory as set forth in claim 7 , wherein each of the memory cells except the dummy transistor is configured to store at least two bits of data.
12. A flash memory device comprising:
first selection transistors each coupled to a plurality of bitlines;
second selection transistors coupled to a common source line;
a plurality of memory cells coupled between the first and second selection transistors and coupled to a plurality of wordlines; and
first dummy transistors provided between the first selection transistors and one of the memory cells which is adjacent to the first selection transistors and second dummy transistors provided between the second selection transistors and one of the memory cells which is adjacent to the second selection transistors, wherein a dummy transistor is conditioned in a floating state during an erase operation.
13. The flash memory as set forth in claim 12 , wherein memory cells coupled to the first and last wordlines, and a deselected bitline of the plurality of bitlines do not exhibit a significant program disturbance effect.
14. The flash memory as set forth in claim 12 , wherein threshold voltages of memory cells coupled to the first and last wordlines and a selected bitline of the plurality of bitlines are equal to threshold voltages of the other memory cells coupled between the first and second selection transistors.
15. The flash memory as set forth in claim 12 , wherein a first dummy wordline coupled to the first dummy transistors and a second dummy wordline coupled to the second dummy transistors are supplied with a power source voltage during program and read operations.
16. The flash memory as set forth in claim 12 , wherein the first and second dummy transistors have the same size as the plurality of memory cells coupled between the first and second selection transistors.
17. The flash memory as set forth in claim 12 , wherein the memory cells except the first and second dummy transistors are configured to store at least two bits of data.
18. A flash memory device comprising:
a first selection transistor coupled to a bitline;
a second selection transistor coupled to a common source line;
a plurality of memory cells coupled between the first and second selection transistors, each memory cell being coupled to a wordline, and
a first dummy memory cell provided between the first selection transistor and one of the memory cells which is adjacent to the first selection transistor and a second dummy memory cell provided between the second selection transistor and one of the memory cells which is adjacent to the second selection transistor,
wherein the first and second dummy memory cells are supplied with a program inhibit voltage during a program operation.
19. The flash memory as set forth in claim 18 , wherein the memory cells which are adjacent to the first and second selection transistor and a deselected bitline of the bitlines are substantially free from an effect of program disturbance.
20. The flash memory as set forth in claim 18 , wherein the first and second dummy memory cells are supplied with a voltage higher than twice a power source voltage and lower than the program inhibit voltage during a program operation.
21. The flash memory as set forth in claim 18 , wherein the first and second dummy memory cells are supplied with a ground voltage during an erase operation and supplied with a read voltage during a read operation.
22. The flash memory as set forth in claim 18 , wherein the first and second dummy memory cells have the same size as the plurality of memory cells coupled between the first and second selection transistors.
23. The flash memory as set forth in claim 18 , wherein each of the memory cells is configured to store at least two bits of data, the first and second dummy memory cells not being configured to store at least two bits of data.