IP Library › Granted Patent US 7,321,167
Granted Patent B2
US 7,321,167 · App. 10/455,906 · Granted Jan 22, 2008

Flex tape architecture for integrated circuit signal ingress/egress

Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,321,167
App. No.
10/455,906
Granted
Jan 22, 2008
Kind
B2
Abstract

In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Claims (13)

1. An apparatus comprising:

an integrated circuit; and

a flexible input/output (I/O) signal routing substrate, coupled to said integrated circuit, including:

a first waveguide signal trace having:

a first signal trace; and

a first electrical reference trace; and

a second waveguide signal trace having:

said first electrical reference trace; and

a second signal trace substantially parallel to said first signal trace and configured such that said first electrical reference trace is disposed between said first signal trace and said second signal trace.

2. The apparatus of claim 1 , wherein said first waveguide signal trace has a second electrical reference trace and the second waveguide signal trace has a third electrical reference trace.

3. The apparatus of claim 1 wherein said first and said second waveguide signal traces are substantially coplanar.

4. The apparatus of claim 1 wherein the I/O signal routing substrate further comprises a first electrical reference layer and a second electrical reference layer, said first and second waveguide signal traces being located between said first electrical reference layer and said second electrical reference layer.

5. The apparatus of claim 4 wherein said first and second electrical reference layers are coupled to at least the first electrical reference trace and/or the second electrical reference trace.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE CONVEYING PARTIES' NAME, PREVIOUSLY RECORDED AT REEL 014157 FRAME 0413. Recorded Mar 22, 2004
From: PARMAR, PRASHANT; KIM, HYUNJUN
To: INTEL CORPORATION
Reel/Frame 015119/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2003
From: ZHONG, DONG; LI, YUAN-LIANG; HE, JIANGQI; KANG, JUNG; PARMAR, PRASHANT; KIM, HYUNJUM; AUERNHEIMER, JOEL
To: INTEL CORPORATION
Reel/Frame 014157/0413 →
Continuity (1)
Related Publication 20040245610A1 · Dec 9, 2004