Silicon-on-insulator differential amplifier circuit
A differential amplifier formed on a silicon-on-insulator substrate, including means to prevent the bodies of its differential input transistors from charging to unwanted potentials in the standby state. In one aspect of the invention, the means takes the form of switching transistors inserted between the differential input transistors and their loads. In another aspect of the invention, the means takes the form of switching transistors inserted between the sources and bodies of the differential input transistors. In another aspect of the invention the means is a regulator section that holds the bodies of the differential input transistors at an appropriate potential level.
1. A differential amplifier circuit formed on a silicon-on-insulator (SOI) substrate, comprising:
a bias section activated and deactivated by an enable signal, outputting a predetermined bias potential when activated, and outputting a first power-supply potential when deactivated;
a first metal-oxide-semiconductor (MOS) transistor of a first channel type, having a source receiving the first power-supply potential, a gate receiving the potential output by the bias section, and a drain connected to a first node;
a source-tied second MOS transistor of the first channel type, having a source connected to the first node, a gate receiving a first differential input signal, and a drain connected to a second node;
a source-tied third MOS transistor of the first channel type, having a source connected to the first node, a gate receiving a second differential input signal, and a drain connected to a third node;
a source-tied fourth MOS transistor of the first channel type, having a source connected to the second node, a gate receiving the enable signal, and a drain connected to a fourth node;
a source-tied fifth MOS transistor of the first channel type, having a source connected to the third node and, a gate receiving the enable signal, and a drain connected to a fifth node;
a source-tied first MOS transistor of a second channel type, having a source receiving a second power-supply potential, a gate connected to the fourth node, and a drain connected to the fourth node;
a source-tied second MOS transistor of the second channel type, having a source receiving the second power-supply potential, a gate connected to the fourth node, and a drain connected to the fifth node; and
an output section connected to the fifth node, generating an output signal from a potential of the fifth node.
2. The differential amplifier circuit of claim 1 , wherein the first channel type is an n-channel type and the second channel type is a p-channel type.
3. The differential amplifier circuit of claim 1 , wherein the first channel type is a p-channel type and the second channel type is an n-channel type.
4. The differential amplifier circuit of claim 1 , wherein the output section comprises:
a source-tied third MOS transistor of the second channel type, having a gate connected to the fifth node; and
a resistor connected in series with the source-tied third MOS transistor of the second channel type.
5. The differential amplifier circuit of claim 1 , further comprising a sixth MOS transistor of the second channel type, having a source receiving the second power-supply potential, a gate receiving the enable signal, and a drain connected to the fifth node.
6. The differential amplifier circuit of claim 5 , wherein the bias section comprises:
three MOS transistors of the second channel type, having respective sources receiving the second power-supply potential, a first one of the three MOS transistors having a gate receiving the enable signal and a drain connected to a sixth node, a second one of the three MOS transistors having a gate and drain connected to a sixth node, a third one of the three MOS transistors having a gate connected to the sixth node and a drain connected to a seventh node;
a resistor;
a seventh MOS transistor of the first channel type, having a source receiving the first power-supply potential through the resistor, a gate connected to the seventh node, and a drain connected to the sixth node;
an eighth MOS transistor of the first channel type, having a source receiving the first power-supply potential, a gate connected to the seventh node, and a drain connected to the seventh node;
an inverter inverting the enable signal; and
a ninth MOS transistor of the first channel type, having a source receiving the first power-supply potential, a gate receiving the inverted enable signal from the inverter, and a drain connected to the seventh node and to the gate of the first MOS transistor of the first channel type.