Microprocessor with independent SIMD loop buffer
An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising an instruction queue. The apparatus further comprises fetch logic configured to fetch instructions; decode logic configured to determine instruction type; a processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the first type of instruction, and an execution unit configured to execute the loop detected by the detection logic.
1. An apparatus, comprising:
detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction;
a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising an instruction queue; and
an execution unit configured to execute the loop detected by the detection logic;
wherein the execution unit has the capability to shut down while the co-processor executes the second type of instruction.
2. The apparatus of claim 1 , further comprising:
fetch logic configured to fetch instructions;
decode logic configured to determine instruction type; and
a processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the first type of instruction.
3. The apparatus of claim 2 , wherein the execution unit is further configured to execute the first type of instruction while the co-processor executes the second type of instruction.
4. The apparatus of claim 2 , wherein the co-processor is further configured to execute instructions of Single Instruction, Multiple Data type and the execution unit configured to execute instructions not of Single Instruction Multiple Data type.
5. The apparatus of claim 2 , wherein the detection logic is further configured to detect one or more nested loops among a set of instructions.
6. The apparatus of claim 2 , further comprising: a load/store unit and a load queue configured to load data for loop operation exclusive of the execution unit and the load/store unit.
7. A system, comprising:
a pipeline in which a plurality of instructions are processed;
detection logic coupled to the pipeline configured to detect a loop in the plurality of instructions, wherein the loop comprises one or more instructions of a first type or a second type;
a co-processor coupled to the pipeline, the co-processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the second type, the co-processor comprising an instruction queue; and
a general execution unit coupled to the pipeline, the general execution unit configured to execute the loop detected by the detection logic;
wherein the general execution unit is adapted to shut down while the co-processor executes the second type of instruction.
8. The system of claim 7 , further comprising:
a processor comprising:
decode logic coupled to the pipeline, the decode logic configured to determine an instruction type of each instruction;
a fetch unit coupled to the pipeline; the fetch unit configured to place instructions of the first type in the general execution unit and instructions of the second type in the instruction queue.
9. The system of claim 8 , wherein the general execution unit is further configured to execute the first type of instruction while the co-processor executes the second type of instruction.
10. The system of claim 8 , wherein the co-processor is further configured to execute instructions of Single Instruction, Multiple Data type and the general execution unit is further configured to execute instructions not of Single Instruction Multiple Data type.
11. The system of claim 7 , wherein the detection logic is further configured to detect one or more nested loops among the plurality of instructions.
12. The system of claim 7 , the system further comprising a load/store unit, and the co-processor further comprising a load queue configured to load data for loop operation exclusive of the general execution unit and the load/store unit.
13. A method, comprising:
detecting a loop within a set of instructions;
determining whether the loop comprises instructions of a first instruction type or a second instruction type;
executing the first instruction type in a general execution unit; and
executing the second instruction type in a co-processor for the second type of instruction;
wherein the general execution unit is configured to shut down during execution of code of the second instruction type in the co-processor.
14. The method of claim 13 , further comprising setting a start pointer and an end pointer, the loop being further defined by the start and end pointers.
15. The method of claim 13 , further comprising executing code of the first instruction type in the general execution unit during execution of code of the second instruction type in the co-processor.
16. The method of claim 13 , further comprising executing code following the loop in the general execution unit during execution of code of the second instruction type in the co-processor.
17. The method of claim 13 , wherein executing the first instruction type further comprises executing instructions that are not Single Instruction, Multiple Data instructions.
18. The method of claim 13 , wherein executing the second instruction type further comprises executing instructions that are Single Instruction, Multiple Data instructions.
19. The method of claim 13 , wherein determining the type of an instruction further comprises decoding the opcode.
20. The system of claim 7 , wherein the system comprises at least one of a battery-operated device and a wireless device.