IP Library Granted Patent US 7,332,434
Granted Patent B2
US 7,332,434 · App. 11/497,428 · Granted Feb 19, 2008

Semiconductor device having diffusion barrier layer containing chrome and method for fabricating the same

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,332,434
App. No.
11/497,428
Granted
Feb 19, 2008
Kind
B2
Abstract

A semiconductor device is provided which is capable of preventing a constitutional material of a diffusion barrier layer from diffusing into a bottom electrode during a high thermal process and of preventing an increase in contact resistance of a contact plug by suppressing mutual diffusions of the constitutional material of the diffusion barrier layer and the contact plug and a method for fabricating the same. The semiconductor device includes a bottom electrode of a capacitor connecting to a substrate through a contact plug; a first diffusion barrier layer disposed on the contact plug, wherein the first diffusion barrier contains Cr therein for preventing mutual diffusions between the bottom electrode and the contact plug; and a second diffusion barrier on the first diffusion barrier for preventing the Cr in the first diffusion layer from diffusing into the bottom electrode; a dielectric layer disposed on the bottom electrode and a top electrode disposed on the dielectric layer.

Claims (27)

1. A method for fabricating a semiconductor device, comprising the steps of:

forming an inter-layer insulating layer on a substrate;

forming a contact hole in the inter-layer insulating layer;

forming a contact plug connecting to the substrate through the contact hole;

forming a first diffusion barrier layer containing Cr on the contact plug and the inter-layer insulating layer;

forming a second diffusion barrier layer on the first diffusion barrier layer for preventing diffusions of the Cr in the first diffusion barrier layer; and

forming a capacitor including a bottom electrode, a dielectric layer and a top electrode on the second diffusion barrier layer,

wherein the first diffusion barrier layer includes Cr x Me 1−x N containing Cr, metal (Me) and N 2 .

2. The method as recited in claim 1 ,

wherein the second diffusion barrier layer is a material selected from the group consisting of IrO 2 , RuO 2 and SrRuO 3 .

3. The method as recited in claim 1 , wherein the step of forming the contact plug includes the steps of:

forming a tungsten layer on the inter-layer insulating layer including the contact hole; and

forming a tungsten plug in the contact hole through an etch-back process.

4. The method as recited in claim 1 , wherein the first diffusion barrier layer is Cr x Me 1−x N containing Cr, metal (Me) and N 2 .

5. The method as recited in claim 4 , wherein the metal (Me) is a substance selected from the group consisting of Ti, Ta and Al.

6. The method as recited in claim 5 , wherein the value of “x” within the Cr x Me 1−x N ranges from about 0.2 mol to about 0.8 mol.

7. The method as recited in claim 1 , further comprising:

forming an ohmic contact layer between the substrate and the contact plug; and

forming a third diffusion barrier layer for preventing a material in the contact plug from diffusing into a space between the ohmic contact layer and the contact plug.

8. The method as recited in claim 7 , wherein the third diffusion barrier layer is a material selected from the group consisting of Ti/TiN, TiN, TaN, TiAlN and TiSiN.

9. A method for fabricating a semiconductor device, comprising the steps of:

forming an inter-layer insulating layer on a substrate;

forming a contact hole in the inter-layer insulating layer;

forming a contact plug connecting to the substrate through the contact hole, wherein the contact plug partially fills the contact hole;

forming a first diffusion barrier layer containing Cr on the contact plug until completely filling the contact hole;

forming a second diffusion barrier layer on the first diffusion barrier layer and the inter-layer insulating layer for preventing diffusions of the Cr in the first diffusion barrier layer; and

forming a capacitor including a bottom electrode, a dielectric layer and a top electrode on the second diffusion barrier layer.

Priority Claims (1)
KR 2002-56461 · Sep 17, 2002 · national
Continuity (2)
Division 1033407200 · Dec 31, 2002
Related Publication 20060270155A1 · Nov 30, 2006