Post polish anneal of atomic layer deposition barrier layers
A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ability to accurately define subsequently formed interconnect structures in the ILD.
1. A method for forming a semiconductor device comprising:
depositing an atomic layer deposition (ALD) barrier film over an interlayer dielectric (ILD) layer;
depositing a copper-containing fill material onto the ALD barrier film;
removing excess portions of the ALD barrier film and the copper-containing fill material from a surface of the ILD layer using a chemical mechanical polishing (CMP) process, thereby exposing at least a portion of the surface;
annealing the ILD layer after the CMP process to outgas an ALD precursor species and/or by-product absorbed by the ILD layer.
2. The method of claim 1 , wherein the ILD layer is further characterized as a porous interlayer dielectric and/or a carbon-doped interlayer dielectric.
3. The method of claim 1 , wherein at least one of the ALD precursor species and/or byproduct is further characterized as a nitrogen-containing precursor species and/or byproduct.
4. The method of claim 3 , wherein the nitrogen-containing precursor species and/or byproduct includes an amine.
5. The method of claim 1 , wherein a precursor used to deposit the atomic layer deposition barrier film includes tantalum.
6. The method of claim 5 , wherein the atomic layer deposition film is further characterized as a tantalum nitride film, and wherein a tantalum-containing precursor used to deposit the tantalum nitride film is selected from a group consisting or pentakis (dimethylamide) tantalum, tertbutylimido (trisdiethylamide) tantalum, pentakis (diethylamide) tantalum, pentakis (ethylmethylamino) tantalum, and tertiarya mylimidotris (dimethylamido) tantalum.
7. The method of claim 1 , wherein annealing is further characterized as annealing in an ambient-containing a gas capable of chemically neutralizing atomic layer deposition precursors and/or by-products absorbed by the interlayer dielectric.
8. The method of claim 7 , wherein the gas is further characterized as an amine neutralizing gas.
9. The method of claim 8 , wherein the amine neutralizing gas contains acetic acid.
10. The method of claim 1 , further comprising depositing a seed layer over the barrier prior to depositing the fill material, wherein removing also removes excess seed layer material.
11. The method of claim 10 further comprising forming an intervening barrier layer between the ILD layer and the upper interconnect.
12. The method of claim 1 further comprising patterning an upper interconnect in a second dielectric deposited overlying the ILD layer.
13. The method of claim 1 , wherein annealing is performed in a furnace at a temperature in a range of 100-400 C.
14. A method for forming a semiconductor device comprising:
depositing an atomic layer deposition (ALD) film over a carbon doped interlayer dielectric;
depositing a fill material onto the ALD film;
removing portions of the ALD film and the fill material from a surface of the carbon doped interlayer dielectric using a chemical mechanical polishing (CMP) process, thereby exposing at least a portion of the surface, and;
annealing the carbon doped interlayer dielectric after the CMP process to neutralize an ALD precursor species and/or by-product absorbed by the carbon doped interlayer dielectric.
15. The method of claim 14 , wherein annealing is further characterized as annealing in an ambient-containing a gas capable of chemically neutralizing the ALD precursors and/or by-products.
16. The method of claim 15 , wherein the gas is further characterized as a dilute amine-neutralizing gas.
17. The method of claim 16 , wherein the amine-neutralizing gas is further characterized as an acetic acid containing gas.