System and method for sensing capacitance change of a capacitive sensor
The present invention relates to systems and methods for sensing capacitance change of a capacitive sensor and for optimizing a capacitive sensing circuit. In an exemplary embodiment, a capacitive sensor may be coupled to an amplifier at floating node. A programming circuit is connected to the floating node for controlling a charge on the floating node. A method of controlling the charge of the floating node is also provided. The method includes applying a first predetermined voltage to a source of a programming transistor, applying a second predetermined voltage to a floating gate of the programming transistor, and applying a third predetermined voltage to a drain of the programming transistor until a charge on the floating gate of the programming transistor reaches a predetermined value. The charge on the floating gate of the programming transistor drives the charge on the floating node to the predetermined value, and thus is controlled.
1. A capacitive sensing circuit comprising:
a capacitive sensor having a sensor output;
a programming circuit having a programming circuit output coupled to the sensor output of the capacitive sensor, the programming circuit having a programming transistor having a source, a floating gate, and a drain, the floating gate being the programming circuit output;
an amplifier having a first amplifier input and an amplifier output, the first amplifier input being coupled to the programming circuit output of the programming circuit; and
a first capacitor having a first terminal and a second terminal, the first terminal coupled to the floating gate of the programming transistor, and the second terminal coupled to a ground.
2. The circuit according to claim 1 , wherein the amplifier is a first order amplifier.
3. The circuit according to claim 1 , wherein the capacitive sensor is a MEMS sensor.
4. The circuit according to claim 1 , wherein the capacitive sensor is a CMUT.
5. The circuit according to claim 1 , the programming circuit further having a programming circuit input, wherein the programming circuit input of the programming circuit is coupled to the amplifier output of the amplifier.
6. The circuit according to claim 1 , wherein the sensor output of the capacitive sensor is coupled to the first amplifier input of the amplifier through a capacitor network.
7. The circuit according to claim 1 , wherein the programming circuit is adapted to control a charge on the first amplifier input of the amplifier.
8. A capacitive sensing circuit comprising:
a capacitive sensor having a sensor output;
a programming circuit having a programming circuit output coupled to the sensor output of the capacitive sensor;
an amplifier having a first amplifier input and an amplifier output, the first amplifier input being coupled to the programming circuit output of the programming circuit;
a buffer circuit having a buffer input coupled to the amplifier output of the amplifier, and a buffer output; and
a comparator having an inverting input and a non-inverting input, the non-inverting input coupled to the buffer output of the buffer;
wherein the inverting input of the comparator is adapted to receive a comparator voltage, and
wherein a comparator output of the comparator is connected to a drain of a programming transistor in the programming circuit.
9. The circuit according to claim 8 , wherein the programming circuit comprises:
a programming transistor having a source, a floating gate and a drain; and
wherein the floating gate is the programming circuit output.
10. The circuit according to claim 9 , further comprising a tunneling capacitor having a first terminal and a second terminal, the first terminal coupled to the first amplifier input of the amplifier, and the second terminal adapted to receive a tunneling voltage.
11. The circuit according to claim 9 , further comprising a first capacitor having a first terminal and a second terminal, the first terminal coupled to the floating gate of the programming transistor, and the second terminal coupled to a ground.
12. The circuit according to claim 8 , wherein the programming circuit comprises a pseudo resistor having a first terminal and a second terminal.
13. The circuit according to claim 12 , wherein the pseudo resistor comprises:
a first transistor having a first source, a first drain, a first gate, and a first well;
a second transistor having a second source, a second drain, a second gate, and a second well;
wherein the second drain, the second gate, the first source and the first well are coupled together;
wherein the second source and the second well are coupled to the first terminal; and
wherein the first drain and the first gate are coupled to the second terminal.
14. The circuit according to claim 8 , wherein the programming circuit comprises an active transistor feedback circuit.
15. A method of controlling a charge on a floating node between a capacitive sensor and an amplifier using a programming transistor having a source, a floating gate, and a drain, the method comprising:
applying a first predetermined voltage signal to the source of the programming transistor;
applying a second predetermined voltage signal to the floating gate of the programming transistor; and
applying a third predetermined voltage signal to the drain of the programming transistor until a charge on the floating gate of the programming transistor reaches a predetermined value,
wherein the charge on the floating gate of the programming transistor drives the charge on the floating node to the predetermined value.
16. A capacitive sensing circuit comprising:
a capacitive sensor having a sensor output;
a programming circuit having a programming circuit output coupled to the sensor output of the capacitive sensor; and
an amplifier having a first amplifier input and an amplifier output, the first amplifier input being coupled to the programming circuit output of the programming circuit;
the programming circuit comprising a pseudo resistor having a first terminal and a second terminal,
the pseudo resistor comprising:
a first transistor having a first source, a first drain, a first gate, and a first well;
a second transistor having a second source, a second drain, a second gate, and a second well;
wherein the second drain, the second gate, the first source and the first well are coupled together;
wherein the second source and the second well are coupled to the first terminal; and
wherein the first drain and the first gate are coupled to the second terminal.