Method for forming a bipolar transistor device with self-aligned raised extrinsic base
View Patent ↗Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.
1. A method of forming a bipolar transistor, said method comprising:
forming a dielectric pad, having a first area dimension, on a substrate;
forming an extrinsic base layer over said dielectric pad and over said substrate;
forming a dielectric layer over said extrinsic base layer;
etching a first opening through said dielectric layer to said extrinsic base layer, wherein said first opening is aligned over said dielectric pad and has a second area dimension that is one of approximately equal to or greater than said first area dimension;
etching a second opening through said extrinsic base layer to said dielectric pad, wherein said second opening is aligned over said dielectric pad and has a third area dimension that is less than said first area dimension; and
selectively removing said extrinsic base layer from all surfaces of said dielectric pad.
2. The method of claim 1 , wherein said forming of said dielectric pad comprises lithographically patterning said dielectric pad such that said first area dimension is a predetermined dimension.
3. The method of claim 1 , further comprising before said etching of said second opening, forming spacers in said first opening on said extrinsic base layer adjacent said dielectric layer to reduce said second area dimension of said first opening.
4. The method of claim 1 , further comprising selectively etching and completely removing said dielectric pad off of said substrate.
5. The method of claim 1 , further comprising forming an emitter in a trench formed by said first opening and said second opening.
6. The method of claim 5 , wherein said forming of said emitter further comprises:
forming a conformal dielectric layer on a bottom surface and sidewalls of said trench;
forming spacers on said conformal dielectric layer such that a portion of said conformal dielectric layer on said bottom surface of said trench remains exposed;
etching said exposed portion of said conformal dielectric layer to said substrate; and
depositing a polycrystalline semiconductor material into said trench onto said substrate.
7. The method of claim 1 , wherein said selectively removing said extrinsic base layer from all surfaces of said dielectric pad comprises performing one of a wet etching process and a reactive ion etching process.
8. A method of forming a transistor, said method comprising:
forming a crystalline silicon germanium layer;
forming a dielectric pad, having a first area dimension, on said crystalline silicon germanium layer;
forming a polycrystalline extrinsic base layer over said dielectric pad and over said crystalline silicon germanium layer;
forming a dielectric layer over said extrinsic base layer;
etching a first opening through said dielectric layer to said extrinsic base layer, wherein said first opening is aligned over said dielectric pad and has a second area dimension that is one of approximately equal to or greater than said first area dimension;
etching a second opening through said extrinsic base layer to said dielectric pad, wherein said second opening is aligned over said dielectric pad and has a third area dimension that is less than said first area dimension; and
selectively removing said polycrystalline extrinsic base layer from all surfaces of said dielectric pad.
9. The method of claim 8 , further comprising before said forming of said crystalline silicon germanium layer:
forming an intrinsic base layer with a crystalline semiconductor material; and
forming an emitter cap layer on said intrinsic base layer, wherein said crystalline silicon germanium layer is formed on said emitter cap layer.
10. The method of claim 9 , wherein said crystalline silicon germanium layer is formed with a predetermined thickness and a predetermined germanium content in order to apply stress to said emitter cap layer and, thereby, enhance carrier mobility and conductivity between said intrinsic base layer and said extrinsic base layer.
11. The method of claim 8 , wherein said forming of said dielectric pad comprises lithographically patterning said dielectric pad such that said first area dimension is a predetermined dimension.
12. The method of claim 8 , further comprising before said etching of said second opening, forming spacers in said first opening on said extrinsic base layer adjacent said dielectric layer so that said second opening is etched with said third area dimension.
13. The method of claim 8 , further comprising selectively etching said dielectric pad off of said crystalline silicon germanium layer; and
etching said crystalline silicon germanium layer from within said second opening selective to said crystalline silicon emitter cap layer to expose said crystalline silicon emitter cap layer.
14. The method of claim 8 , further comprising forming an emitter in a trench formed by said first opening and said second opening.
15. The method of claim 14 , wherein said forming of said emitter further comprises:
forming a conformal dielectric layer on a bottom surface and sidewalls of said trench;
forming dielectric spacers on said conformal dielectric layer such that a portion of said conformal dielectric layer on said bottom surface of said trench remains exposed;
etching said exposed portion of said conformal dielectric layer to said emitter cap layer; and
depositing a polycrystalline semiconductor material into said trench onto said emitter cap layer.
16. The method of claim 8 , wherein said selectively removing said polycrystalline extrinsic base layer from all surfaces of said dielectric pad comprises performing one of a wet etching process and a reactive ion etching process.
17. A method of forming a transistor, said method comprising:
forming an emitter cap layer;
forming a dielectric pad having a first area dimension on said emitter cap layer;
forming an extrinsic base layer over said dielectric pad;
forming a dielectric layer over said extrinsic base layer;
etching a first opening through said dielectric layer to said extrinsic base layer, wherein said first opening is aligned over said dielectric pad and has a second area dimension that is one of approximately equal to or greater than said first area dimension;
etching a second opening through said extrinsic base layer to said dielectric pad, wherein said second opening is aligned over said dielectric pad and has a third area dimension that is less than said first area dimension; and
selectively removing said extrinsic base layer from all surfaces of said dielectric pad.
18. The method of claim 17 , further comprising before said forming of said emitter cap layer,
forming an intrinsic base layer with a crystalline semiconductor material, wherein said emitter cap layer is formed on said intrinsic base layer.
19. The method of claim 18 , wherein said emitter cap layer comprises a crystalline silicon material, wherein said extrinsic base layer if formed with a polycrystalline silicon germanium material with a predetermined germanium content in order to apply stress to said emitter cap layer and, thereby, enhance carrier mobility and conductivity between said intrinsic base layer and said extrinsic base layer.
20. The method of claim 17 , wherein said forming of said dielectric pad comprises lithographically patterning said dielectric pad such that said first area dimension is a predetermined dimension.
21. The method of claim 17 , further comprising before said etching of said second opening, forming spacers in said first opening on said extrinsic base layer adjacent said dielectric layer so that said second opening is etched with said third area dimension.
22. The method of claim 17 , further comprising selectively etching and completely removing said dielectric pad off of said emitter cap layer.
23. The method of claim 17 , further comprising forming an emitter in a trench formed by said first opening and said second opening.
24. The method of claim 23 , wherein said forming of said emitter comprises:
forming a conformal dielectric layer on a bottom surface and sidewalls of said trench;
forming dielectric spacers on said conformal dielectric layer such that a portion of said conformal dielectric layer on said bottom surface of said trench remains exposed;
etching said exposed portion of said conformal dielectric layer to said emitter cap layer; and
depositing a polycrystalline semiconductor material into said trench onto said emitter cap layer.