Applying epitaxial silicon in disposable spacer flow
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.
1. Intermediate active transistor structures for a semiconductor memory device comprising:
transistor gates having generally vertical sidewalls in a memory array section and in periphery sections;
n-type dopants in n-channel devices and p-type conductive dopants in p-channel devices at a first level of exposed silicon regions defined as active area regions of the transistor gates;
spacers on the generally vertical sidewalls of the transistor gates having a thickness that is less than half the spacing between the transistor gates in the memory array section;
epitaxial silicon completely covering the exposed silicon regions to form epitaxial silicon extension regions; and
n-type source/drain regions of n-channel devices and p-type source/drain regions of p-channel devices at a second level of the exposed silicon regions and the epitaxial silicon extension regions.
2. The intermediate active transistor structures as recited in claim 1 , wherein the spacers comprise oxide.
3. The intermediate active transistor structures as recited in claim 1 , wherein the epitaxial silicon comprises epitaxial silicon germanium.
4. Intermediate active transistor structures for a semiconductor memory device comprising:
transistor gates having generally vertical sidewalls in a memory array section and in periphery sections;
n-type dopants in n-channel devices and p-type conductive dopants in p-channel devices at a first level of exposed silicon regions defined as active area regions of the transistor gates;
spacers on the generally vertical sidewalls of the transistor gates having a thickness that is more than half the spacing between the transistor gates in the memory array section;
epitaxial silicon completely covering the exposed silicon regions to form epitaxial silicon extension regions; and
n-type source/drain regions of n-channel devices and p-type source/drain regions of p-channel devices at a second level of the exposed silicon regions and the epitaxial silicon extension regions.
5. The intermediate active transistor structures as recited in claim 4 , wherein the spacers comprise oxide.
6. The intermediate active transistor structures as recited in claim 4 , wherein the epitaxial silicon comprises epitaxial silicon germanium.