Method, apparatus, and system for active refresh management
A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
1. A memory device comprising:
an array of memory cells; and
at least one readable and writable refresh start/end data storage element to store a refresh start value indicating a specific point within the array of memory cells for starting a refresh operation.
2. The memory device of claim 1 , wherein the at least one readable and writable refresh start/end data storage element is further to store a refresh end value indicating a specific point within the array of memory cells for ending a refresh operation.
3. The memory device of claim 1 , wherein the array of memory cells is arranged in one or more banks.
4. The memory device of claim 2 , wherein the refresh start value is an address corresponding to a location in memory where a refresh cycle begins.
5. The memory device of claim 3 , wherein each bank corresponds to one refresh start/end data storage element.
6. The memory device of claim 4 , wherein the refresh end value is an address corresponding to a location in memory where the refresh cycle ends.
7. The memory device of claim 4 , wherein the refresh end value is a number corresponding to a number of locations in memory that are to be refreshed during a refresh cycle.
8. A system comprising:
a processor;
a memory controller device coupled to the processor, the memory controller device capable of sending a refresh start address and a refresh end address; and
a memory device coupled to the memory controller device, the memory device capable of receiving and storing the refresh start address and the refresh end address.
9. The system of claim 8 , wherein the memory device is further capable of contiguously refreshing memory locations between the refresh start address and the refresh end address.
10. The system of claim 8 , wherein the memory device is capable of receiving the refresh start address and the refresh end address over a data bus.
11. The system of claim 8 , wherein the memory device is capable of receiving the refresh start address and the refresh end address over an address bus.
12. The system of claim 9 , wherein the memory device is a DRAM memory device.
13. The system of claim 9 , wherein the memory device is a DDR memory device.
14. A memory device comprising:
an array of memory cells;
at least one readable and writable data storage element to store a refresh start address indicating a specific point within the array of memory cells for starting a refresh operation; and
at least one readable and writable data storage element to store a refresh end address indicating a specific point within the array of memory cells for ending a refresh operation.
15. The memory device of claim 14 , wherein the array of memory cells is arranged in one or more banks.
16. The memory device of claim 15 , wherein each bank corresponds to a readable and writable data storage element to store a start refresh address and a readable and writable data storage element to store an end refresh address.