Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal
An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.
1. An instruction fetch control apparatus that controls predicted return address selection for a processor, the instruction fetch control apparatus having a branch history in which an instruction address of a branch instruction and an address of a branched-to instruction for use when a branch is taken are registered as a set of data for the branch instruction, and a return address stack storing a returned-to instruction address of a subroutine when a subroutine call instruction is completely executed, comprising:
an entry designation unit designating, when an instruction fetched from a main storage device and detected by the instruction fetch control apparatus as a hit in the branch history is a return instruction of a subroutine, an entry in a plurality of entries in the return address stack as an entry storing a return address of the subroutine return instruction, the entry designation unit receiving
a call flag and a return flag for the instruction detected as a hit in the branch history,
a signal indicating whether the completed instruction is a subroutine call instruction,
a signal indicating whether the completed instruction is a subroutine return instruction,
an instruction refetch signal, and
a value currently designated by the entry designation unit,
the entry designation unit computing, based on the received flags and signals, the entry to be designated in the return address stack, the branch history and return address stack being searched in synchronization with the instruction fetch rather than pushing and popping of the return address stack, the pushing and popping being performed when execution of a subroutine call or return instruction is completed, thereby adjusting the timing between an instruction fetch performed speculatively in advance and the completion of the previously fetched instruction when completing execution of a branch instruction that corresponds with the subroutine call or return and predicting the subroutine call or return, wherein
a next instruction is fetched using the return address stored in said designated entry if the return address stack is not empty, and
an entry address corresponding to a stack position designated by the entry designation unit is adopted as a subroutine call or return address prediction, and
wherein said fetched instruction is not to be executed, and the appropriate instruction to execute has to be fetched, said entry designation unit pushes the designated entry onto the top of the return address stack.
2. An instruction fetch control apparatus that controls predicted return address selection for a processor, the instruction fetch control apparatus having a branch history in which an instruction address of a branch instruction and an address of a branched-to instruction for use when a branch is taken are registered as a set of data for the branch instruction, and a return address stack storing a returned-to instruction address of a subroutine when a subroutine call instruction is completely executed, comprising:
an entry designation unit designating, when an instruction fetched from a main storage device and detected by the instruction fetch control apparatus as a hit in the branch history is a return instruction of a subroutine, an entry in a plurality of entries in the return address stack as an entry storing a return address of the subroutine return instruction, the entry designation unit receiving
a call flag and a return flag for the instruction detected as a hit in the branch history,
a signal indicating whether the completed instruction is a subroutine call instruction,
a signal indicating whether the completed instruction is a subroutine return instruction,
an instruction refetch signal, and
a value currently designated by the entry designation unit,
the entry designation unit computing, based on the received flags and signals, the entry to be designated in the return address stack, the branch history and return address stack being searched in synchronization with the instruction fetch rather than pushing and popping of the return address stack, the pushing and popping being performed when execution of a subroutine call or return instruction is completed, thereby adjusting the timing between an instruction fetch performed speculatively in advance and the completion of the previously fetched instruction when completing execution of a branch instruction that corresponds with the subroutine call or return and predicting a subroutine call or return, wherein
a next instruction is fetched using the return address stored in said designated entry if the return address stack is not empty, and
an entry address corresponding to a stack position designated by the entry designation unit is adopted as a subroutine call or return address prediction, and
wherein when the return address stack is empty and said entry designation unit designates an invalid entry in the return address stack, an instruction is fetched using a branched-to address stored in the branch history.
3. An instruction fetch control apparatus that controls predicted return address selection for a processor, the instruction fetch control apparatus having a branch history in which an instruction address of a branch instruction and an address of a branched-to instruction for use when a branch is taken are registered as a set of data for the branch instruction, and a return address stack storing a returned-to instruction address of a subroutine when a subroutine call instruction is completely executed, comprising:
an entry designation unit designating, when an instruction fetched from a main storage device and detected by the instruction fetch control apparatus as a hit in the branch history is a return instruction of a subroutine, an entry in a plurality of entries in the return address stack as an entry storing a return address of the subroutine return instruction, the entry designation unit receiving
a call flag and a return flag for the instruction detected as a hit in the branch history,
a signal indicating whether the completed instruction is a subroutine call instruction,
a signal indicating whether the completed instruction is a subroutine return instruction,
an instruction refetch signal, and
a value currently designated by the entry designation unit,
the entry designation unit computing, based on the received flags and signals, the entry to be designated in the return address stack, the branch history and return address stack being searched in synchronization with the instruction fetch rather than pushing and popping of the return address stack, the pushing and popping being performed when execution of a subroutine call or return instruction is completed, thereby adjusting the timing between an instruction fetch performed speculatively in advance and the completion of the previously fetched instruction when completing execution of a branch instruction that corresponds with the subroutine call or return and predicting the subroutine call or return, wherein
a next instruction is fetched using the return address stored in said designated entry if the return address stack is not empty, and
an entry address corresponding to a stack position designated by the entry designation unit is adopted as a subroutine call or return address prediction, and
wherein said entry designation unit can designate a non-existing virtual entry when the return address stack is empty, causing the instruction fetch control apparatus to search the branch history in order to find a predicted return address.