Memory and driving method of the same
View Patent ↗According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
1. A memory comprising:
a memory cell;
a clocked inverter including at least a transistor; and
a column decoder,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line, and
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder.
2. A memory according to claim 1 , wherein the transistor included in the clocked inverter is a thin film transistor.
3. A memory according to claim 1 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes an oxide film.
4. A memory according to claim 1 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes a ferroelectric substance.
5. A memory according to claim 1 , wherein the memory cell includes six transistors.
6. A memory according to claim 1 , wherein the memory cell includes five transistors.
7. A memory according to claim 1 , wherein the memory cell includes four transistors and two resistors.
8. A memory according to claim 1 , wherein the memory cell includes four transistors and a resistor.
9. A memory according to claim 1 , wherein the memory is a Read Only Memory.
10. An electric apparatus including the memory according to claim 1 .
11. A memory comprising:
a memory cell;
a clocked inverter including at least a transistor;
a column decoder; and
an inverter,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line, and
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder through the inverter.
12. A memory according to claim 11 , wherein the transistor included in the clocked inverter is a thin film transistor.
13. A memory according to claim 11 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes an oxide film.
14. A memory according to claim 11 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes a ferroelectric substance.
15. A memory according to claim 11 , wherein the memory cell includes six transistors.
16. A memory according to claim 11 , wherein the memory cell includes five transistors.
17. A memory according to claim 11 , wherein the memory cell includes four transistors and two resistors.
18. A memory according to claim 11 , wherein the memory cell includes four transistors and a resistor.
19. A memory according to claim 11 , wherein the memory is a Read Only Memory.
20. An electric apparatus including the memory according to claim 11 .
21. A memory comprising:
a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder; and
a Read/Write circuit including a second switch and a third switch,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to a Read Enable signal line, and
a gate electrode of a third transistor included in the third switch is electrically connected to a Write Enable signal line.
22. A memory according to claim 21 , wherein the transistor included in the clocked inverter is a thin film transistor.
23. A memory according to claim 21 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes an oxide film.
24. A memory according to claim 21 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes a ferroelectric substance.
25. A memory according to claim 21 , wherein the memory cell includes six transistors.
26. A memory according to claim 21 , wherein the memory cell includes five transistors.
27. A memory according to claim 21 , wherein the memory cell includes four transistors and two resistors.
28. A memory according to claim 21 , wherein the memory cell includes four transistors and a resistor.
29. A memory according to claim 21 , wherein each of the first switch, the second switch and the third switch is an analog switch.
30. A memory according to claim 21 , wherein the memory is a Random Access Memory.
31. An electric apparatus including the memory according to claim 21 .
32. A memory comprising:
a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder; and
a Read/Write circuit including a second switch, a third switch, a first logic circuit and a second logic circuit,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to an output node of the first logic circuit,
a gate electrode of a third transistor included in the third switch is electrically connected to an output node of the second logic circuit,
a first input node of the first logic circuit is electrically connected to a Read Enable signal line,
a second output node of the first logic circuit is electrically connected to a Chip Enable signal line,
a first input node of the second logic circuit is electrically connected to a Write Enable signal line, and
a second input node of the second logic circuit is electrically connected to a Chip Enable signal line.
33. A memory according to claim 32 , wherein the transistor, included in the clocked inverter is a thin film transistor.
34. A memory according to claim 32 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes an oxide film.
35. A memory according to claim 32 , wherein the memory cell includes a transistor and a capacitor, and wherein the capacitor includes a ferroelectric substance.
36. A memory according to claim 32 , wherein the memory, cell includes six transistors.
37. A memory according to claim 32 , wherein the memory cell includes five transistors.
38. A memory according to claim 32 , wherein the memory cell includes four transistors and two resistors.
39. A memory according to claim 32 , wherein the memory cell includes four transistors and a resistor.
40. A memory according to claim 32 , wherein each of the first switch, the second switch and the third switch is an analog switch.
41. A memory according to claim 32 , wherein each of the first logic circuit and the second logic circuit is NOR.
42. A memory according to claim 32 , wherein the memory is a Random Access Memory.
43. An electric apparatus including the memory according to claim 32 .
44. A memory comprising:
a memory cell;
a clocked inverter including at least a transistor; and
a column decoder,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder, and
the memory cell includes a transistor having two gates, one of the two gates is a floating gate.
45. A memory according to claim 44 , wherein the transistor included in the clocked inverter is a thin film transistor.
46. A memory according to claim 44 , wherein the memory is a Read Only Memory.
47. An electric apparatus including the memory according to claim 44 .
48. A memory comprising:
a memory cell;
a clocked inverter including at least a transistor;
a column decoder; and
an inverter,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder through the inverter, and
the memory cell includes a transistor having two gates, one of the two gates is a floating gate.
49. A memory according to claim 48 , wherein the transistor included in the clocked inverter is a thin film transistor.
50. A memory according to claim 48 , wherein the memory is a Read Only Memory.
51. An electric apparatus including the memory according to claim 48 .
52. A memory comprising:
a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder; and
a Read/Write circuit including a second switch and a third switch,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter,
an output node of the clocked inverter is electrically connected to a data line through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to a Read Enable signal line,
a gate electrode of a third transistor included in the third switch is electrically connected to a Write Enable signal line, and
the memory cell includes a transistor having two gates, one of the two gates is a floating gate.
53. A memory according to claim 52 , wherein the transistor included in the clocked inverter is a thin film transistor.
54. A memory according to claim 52 , wherein each of the first switch, the second switch and the third switch is an analog switch.
55. A memory according to claim 52 , wherein the memory is a Random Access Memory.
56. An electric apparatus including the memory according to claim 52 .
57. A memory comprising:
a memory cell;
a selector having a first switch and a clocked inverter including at least a transistor;
a column decoder; and
a Read/Write circuit including a second switch, a third switch, a first logic circuit and a second logic circuit,
wherein:
the memory cell is electrically connected to a bit line and a word line,
the bit line is electrically connected to an input node of the clocked inverter, an output node of the clocked inverter is electrically connected to a data line
through the second switch,
the bit line is electrically connected to the data line through the first switch and the third switch,
a gate electrode of the transistor included in the clocked inverter is electrically connected to the column decoder,
a gate electrode of a first transistor included in the first switch is electrically connected to the column decoder,
a gate electrode of a second transistor included in the second switch is electrically connected to an output node of the first logic circuit,
a gate electrode of a third transistor included in the third switch is electrically connected to an output node of the second logic circuit,
a first input node of the first logic circuit is electrically connected to a Read Enable signal line,
a second output node of the first logic circuit is electrically connected to a Chip Enable signal line,
a first input node of the second logic circuit is electrically connected to a Write Enable signal line,
a second input node of the second logic circuit is electrically connected to a Chip Enable signal line, and
the memory cell includes a transistor having two gates, one of the two gates is a floating gate.
58. A memory according to claim 57 , wherein the transistor included in the clocked inverter is a thin film transistor.
59. A memory according to claim 57 , wherein each of the first switch, the second switch and the third switch is an analog switch.
60. A memory according to claim 57 , wherein each of the first logic circuit and the second logic circuit is NOR.
61. A memory according to claim 57 , wherein the memory is a Random Access Memory.
62. An electric apparatus including the memory according to claim 57 .