Apparatus and method for multiple-gate semiconductor device with angled sidewalls
View Patent ↗A multiple-gate transistor has an active region with a side that forms an interior angle with the base of the active region of less than 80°. A process for fabricating a FinFET includes the steps of etching a silicon-on-insulator wafer to form an active region, including the source, channel, and drain, with vertically angled sidewalls.
1. A transistor comprising:
a mesa formed in an active layer of a substrate, the mesa having a trapezoidal cross section and having sidewalls that form an angle from about 45 degrees to about 70 degrees to vertical;
first and second source/drain regions formed within the mesa;
a channel region in the mesa interjacent the first and second source/drain regions;
a gate dielectric overlying the channel region along the sidewalls and a top surface of the mesa; and
a gate electrode overlying the gate dielectric.
2. The transistor of claim 1 wherein one of said source/drain regions is shared with a second transistor.
3. The transistor of claim 1 wherein said mesa is formed from an active layer of a semiconductor on insulator (SOI) substrate.
4. The transistor of claim 1 wherein said active layer is formed of a material selected from the group consisting essentially of silicon, germanium, strained silicon, carbon, and combinations thereof.
5. The transistor of claim 1 wherein said mesa is between about 200 Angstroms and 1000 Angstroms in thickness.
6. The transistor of claim 1 wherein the top surface of said mesa has a width of about 200 Angstroms.
7. An integrated circuit comprising:
a substrate;
a buried oxide layer formed on said substrate; and
an active layer formed on said buried oxide layer, the active layer having been formed into a series of mesas, each such mesa having a generally trapezoidal cross-section and having sidewalls that form an interior angle, relative to vertical, of less than 80 degrees;
at least one of said mesas having:
first and second source/drain regions formed therein;
a channel region formed therein interjacent the first and second source/drain regions;
a gate dielectric formed over the channel region; and
a gate electrode formed over the gate dielectric, the gate dielectric further overlying a second channel region formed in a second mesa.
8. The integrated circuit of claim 7 wherein said gate electrode comprises polysilicon.
9. The integrated circuit of claim 7 wherein said interior angles are about 70 degrees.
10. The integrated circuit of claim 7 wherein said interior angles are about 45 degrees.
11. The integrated circuit of claim 7 further comprising:
a third source/drain region formed in said at least one mesa;
a second channel region formed interjacent said second and third source/drain regions;
a second gate dielectric formed over the second channel region; and
a second gate electrode formed over the second gate dielectric.
12. The integrated circuit of claim 11 wherein the gate dielectric and the second gate dielectric are formed in a single continuous dielectric layer.
13. A transistor comprising:
a semiconductor on insulator (SOI) substrate;
a mesa formed in an active layer of the SOI substrate, wherein the mesa has sidewalls forming an angle to vertical from about 45 degrees to about 70 degrees;
first and second source/drain regions formed within the mesa;
a channel region in the mesa interjacent to the first and second source/drain regions; and
a gate region overlying the channel region along the sidewalls and a top surface of the mesa.
14. The transistor of claim 13 wherein said gate region comprises:
a gate electrode deposited onto a gate dielectric layer, the gate dielectric layer formed over the channel region.
15. The transistor of claim 13 further comprising:
a second transistor, wherein the second transistor shares the first and second source/drain regions.
16. The transistor of claim 13 wherein the mesa has a trapezoidal cross-section.
17. The transistor of claim 13 wherein the active layer is formed from a material selected from the group consisting essentially of:
silicon;
germanium;
strained silicon;
carbon; and
a combination of one or more of: silicon, germanium, strained silicon, and carbon.
18. The transistor of claim 13 wherein the mesa has a thickness measuring between about 200 Angstroms and 1000 Angstroms.
19. The transistor of claim 13 wherein the top surface of the mesa has a width of about 200 Angstroms.
20. An integrated circuit comprising:
a semiconductor on insulator (SOI) substrate;
one or more mesas formed in an active layer of the SOI substrate, wherein each of the one or more mesas has a generally trapezoidal cross-section and sidewalls forming an interior angle to vertical of less than 80 degrees;
first and second source/drain regions formed in at least one of the one or more mesas;
a channel region formed interjacent to the first and second source/drain regions;
a gate region formed over the channel region, wherein the gate region overlies a second channel region formed in a second of the one or more mesas.
21. The integrated circuit of claim 20 wherein said gate region comprises:
a gate dielectric deposited over the channel region and the second channel region; and
a gate electrode formed over the gate dielectric.
22. The integrated circuit of claim 21 wherein said gate electrode comprises polysilicon.
23. The integrated circuit of claim 20 wherein said interior angles comprise one of:
about 70 degrees; and
about 45 degrees.
24. The integrated circuit of claim 20 further comprising:
a third source/drain region formed in the one or more mesas;
a second channel region formed interjacent the second and third source/drain regions;
a second gate dielectric formed over the second channel region, said second gate dielectric having a second gate electrode formed thereon.
25. The integrated circuit of claim 24 wherein a gate dielectric of the gate region and the second gate dielectric are formed in a single continuous dielectric layer.