Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
View Patent ↗A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
1. A semiconductor device, comprising:
a substrate;
a plurality of logic devices located over the substrate;
an insulating layer located over the plurality of logic devices and including a plurality of recesses exposing underlying ones of the plurality of logic devices;
an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen;
a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and
a conductive layer located over the barrier layer including within the plurality of recesses.
2. The semiconductor device recited in claim 1 wherein the enlarged grain size of the plasma-treated agglutinating layer is about 20% larger than prior to plasma treatment.
3. The semiconductor device recited in claim 1 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a sheet resistance ranging between about 70 Ω/nm 2 and about 130 Ω/nm 2 .
4. The semiconductor device recited in claim 1 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a contact resistance ranging between about 6 Ω/nm 2 and about 9 Ω/nm 2 .
5. The semiconductor device recited in claim 4 wherein the contact has a sheet resistance ranging between about 70 Ω/nm 2 and about 130 Ω/nm 2 .
6. The semiconductor device recited in claim 1 wherein the agglutinating layer comprises a material selected from the group consisting of: Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.
7. The semiconductor device recited in claim 1 wherein the agglutinating layer has a thickness ranging between about 100 angstroms and about 160 angstroms.
8. The semiconductor device recited in claim 1 wherein the barrier layer comprises a material selected from the group consisting of: Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.
9. The semiconductor device recited in claim 1 wherein the barrier layer includes a plurality of plasma densified TiN layers.
10. A semiconductor device, comprising:
a logic device located over a substrate;
an insulating layer located over the logic device, wherein a recess in the insulating layer exposes at least a portion of the logic device;
an agglutinating layer located over the insulating layer and within the recess, the agglutinating layer having an enlarged grain size due to plasma treatment, wherein the enlarged grain size of the plasma-treated agglutinating layer is about 20% larger than prior to plasma treatment;
a barrier layer located over the plasma-treated agglutinating layer and within the recess; and
a conductive layer located over the barrier layer and within the recess.
11. The semiconductor device recited in claim 10 wherein the agglutinating layer has the enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen.
12. The semiconductor device recited in claim 10 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a sheet resistance ranging between about 70 Ω/nm 2 and about 130 Ω/nm 2 .
13. The semiconductor device recited in claim 10 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a contact resistance ranging between about 6 Ω/nm 2 and about 9 Ω/nm 2 .
14. The semiconductor device recited in claim 13 wherein the contact has a sheet resistance ranging between about 70 Ω/nm 2 and about 130 Ω/nm 2 .
15. The semiconductor device recited in claim 10 wherein the agglutinating layer comprises a material selected from the group consisting of: Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.
16. The semiconductor device recited in claim 10 wherein the agglutinating layer has a thickness ranging between about 100 angstroms and about 160 angstroms.
17. The semiconductor device recited in claim 10 wherein the barrier layer comprises a material selected from the group consisting of: Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.
18. The semiconductor device recited in claim 10 wherein the barrier layer includes a plasma-densified layer.
19. The semiconductor device recited in claim 10 wherein the barrier layer includes a plurality of plasma-densified TiN layers.
20. A semiconductor device, comprising:
a logic device located over a substrate;
an insulating layer located over the logic device and having a recess that exposes at least a portion of the logic device; and
a contact located within the recess and comprising:
an agglutinating layer having an enlarged grain size due to plasma treatment;
a barrier layer located over the plasma-treated agglutinating layer; and
a conductive layer located over the barrier layer;
wherein the contact has at least one of:
a sheet resistance ranging between about 70 Ω/nm 2 and about 130 Ω/nm 2 ; and
a contact resistance ranging between about 6 Ω/nm 2 and about 9 Ω/nm 2 .