Non-volatile memory device having uniform programming speed
Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third group of memory cells respectively connected to the remaining word lines other than the first and last word lines. Accordingly, the program speed of the first and second groups of the memory cells can be improved.
1. A non-volatile memory device, comprising:
a first select transistor coupled to a bit line;
a second select transistor coupled to a common source line; and
a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell coupled to a word line, the memory cells defining a first memory cell that is provided on one end of the array and having a first memory cell size, a last memory cell that is provided in an opposing end of the array and having a second memory cell size, and remaining memory cells provided between the first and last memory cells, each of the remaining memory cells having a third memory cell size,
wherein both of the first and second memory cell sizes are greater than the third memory cell size.
2. The non-volatile memory device as claimed in claim 1 , wherein the first memory cell size is at least 10% greater than the third memory size, and the second memory size is at least 12% greater than the third memory size.
3. The non-volatile memory device as claimed in claim 1 , wherein the first memory cell is adjacent to the second select transistor and the second memory cell is adjacent to t he first select transistor.
4. The non-volatile memory device as claimed in claim 1 , wherein the first memory cell is adjacent to the first select transistor and the second memory cell is adjacent to the second select transistor.
5. The non-volatile memory device as claimed in claim 1 , wherein the plurality of memory cells are a multi-level cell.
6. The non-volatile memory device as claimed in claim 1 , wherein the first memory cell size is at least 10% greater than the third memory cell size, and the second memory size cell is at least 12% greater than the third memory cell size, so that threshold voltages associated with first and last memory cells are increased to improve the uniformity of a program operation speed of the memory cells and decrease a program threshold distribution.
7. A non-volatile memory device, comprising:
a first select transistor coupled to a bit line;
a second select transistor coupled to a common source line; and
a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell coupled to a word line,
wherein the cell size of a first group of memory cells is greater than that of a second group of the memory cells, and
wherein the first group of the memory cells comprises a single memory cell and is nearest to the first select transistor.
8. The non-volatile memory device as claimed in claim 7 , wherein the size of the first group of the memory cells is at least 12% greater than the size of the second group of the memory cells.
9. A non-volatile memory device, comprising:
a first select transistor coupled to a bit line;
a second select transistor coupled to a common source line; and
a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell coupled to a word line,
wherein the cell size of a first group of memory cells is greater than that of a second group of the memory cells, and
wherein the first group of the memory cells is nearest to the second select transistor.
10. The non-volatile memory device as claimed in claim 7 , wherein the plurality of memory cells are a multi-level cell.
11. A non-volatile memory device, comprising:
a first select transistor coupled to a bit line;
a second select transistor coupled to a common source line; and
a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell being coupled to a word line, the memory cells defining a first memory cell that is the nearest to the first select transistor and having a first memory cell size, a second memory cell that is the nearest to the second select transistor and having a second memory cell size, and remaining memory cells provided between the first and last memory cells, each of the remaining memory cells having a third memory cell size,
wherein both of the first and second memory cell sizes are greater than the third memory cell size to increase threshold voltages associated with the first and second memory cells.
12. The non-volatile memory device as claimed in claim 9 , wherein the size of the first group of the memory cells is at least 12% greater than the size of the second group of the memory cells.
13. The non-volatile memory device as claimed in claim 9 , wherein the first group of the memory cells comprises only a single memory cell and is nearest to the first select transistor.
14. The non-volatile memory device as claimed in claim 9 , wherein the plurality of memory cells are a multi-level cell.