IP Library › Granted Patent US 7,366,025
Granted Patent B2
US 7,366,025 · App. 10/864,500 · Granted Apr 29, 2008

Reduced power programming of non-volatile cells

Assignee: Saifun Semiconductors Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,366,025
App. No.
10/864,500
Filed
Jun 10, 2004
Granted
Apr 29, 2008
Kind
B2
Examiner
MAI, SON LUU
Art Unit
2827
USPC
365/185.28
Abstract

Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Claims (10)

1. A method comprising: programming a non-volatile memory cell utilizing only substantially transient current flowing from a positive supply to ground through a memory array in which said cell forms a part.

2. The method of claim 1 and wherein said programming comprises: disconnecting a source of the non-volatile memory cell from a ground voltage; and after said source is disconnected, providing a programming voltage to a drain of said cell.

3. The method according to claim 2 and wherein said disconnecting comprises disconnecting a ground supply from a global bit line.

4. The method according to claim 2 and wherein said disconnecting comprises disconnecting a local bit line forming said source from a global bit line carrying said ground voltage.

5. The method of claim 1 and wherein said programming comprises: providing a programming voltage to a drain of said cell; and after said drain voltage is applied, disconnecting a source of the non-volatile memory cell from a ground voltage.

6. The method according to claim 5 and wherein said disconnecting comprises disconnecting a ground supply from a global bit line.

7. The method according to claim 5 and wherein said disconnecting comprises disconnecting a local bit line forming said source from a global bit line carrying said ground voltage.

8. The method of claim 1 wherein said non-volatile memory cell is art NROM cell.

9. The method of claim 1 wherein said memory array is a segmented virtual ground array.

10. The method of claim 9 wherein said array has isolation slices therein.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2004
From: MAAYAN, EDUARDO
To: SAIFUN SEMICONDUCTORS LTD.
Reel/Frame 015457/0737 →
Continuity (1)
Related Publication 20050276118A1 · Dec 15, 2005