IP Library Granted Patent US 7,369,393
Granted Patent B2
US 7,369,393 · App. 11/102,542 · Granted May 6, 2008

Electrostatic chucks having barrier layer

Assignee: Saint-Gobain Ceramics & Plastics, Inc.
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Quick Facts
Patent No.
US 7,369,393
App. No.
11/102,542
Granted
May 6, 2008
Kind
B2
Abstract

An electrostatic chuck for supporting a semiconductor wafer, including: a chuck body having a dielectric region and an insulating region, the insulating region having a higher electrical resistivity than the dielectric region, an electrode embedded in the chuck body, and a barrier layer provided between dielectric region and the insulating region.

Claims (23)

1. An electrostatic chuck for supporting a semiconductor wafer, comprising:

a chuck body including a dielectric region comprising AlN and an insulating region comprising AlN, the insulating region having a higher electrical resistivity than the dielectric region;

an electrode embedded in the chuck body; and

a barrier layer provided between dielectric region and the insulating region, wherein the barrier layer separates the dielectric region from the insulating region to prevent chemical reactions between the dielectric region and the insulating region, or to prevent diffusion of material between the dielectric region and the insulating region.

2. The electrostatic chuck of claim 1 , wherein at least one of the dielectric region and the insulating region includes a resistivity-modifying additive for modifying electrical resistivity, the barrier layer being effective to prevent diffusion of said resistivity-modifying additive between the insulating region and the dielectric region.

3. The electrostatic chuck of claim 2 , wherein the resistivity-modifying additive is provided in the insulating region, and comprises at least one component from the group consisting of magnesium and lithium.

4. The electrostatic chuck of claim 1 , wherein the chuck body has first and second opposite major surfaces, the first surface defining a chucking surface for receiving a semiconductor wafer, the second surface defining a backside of the chuck body, the dielectric region defining the chucking surface and extending between the chucking surface and the electrode.

5. The electrostatic chuck of claim 4 , wherein the insulating region is present between the electrode and the backside of the chuck body.

6. The electrostatic chuck of claim 4 , further comprising a second dielectric region extending between the insulating region and the backside of the chuck body.

7. The electrostatic chuck of claim 1 , further comprising a second barrier layer provided between the insulating region and the second dielectric region.

8. The electrostatic chuck of claim 1 , wherein the barrier layer extends between the electrode and the insulating region thereby isolating the electrode from the insulating region.

9. The electrostatic chuck of claim 8 , wherein the electrode is embedded in the barrier layer such that the barrier layer isolates the electrode from both the insulating region and the dielectric region.

10. The electrostatic chuck of claim 1 , wherein the electrode comprises at least one component from the group consisting of molybdenum and tungsten.

11. The electrostatic chuck of claim 1 , wherein the insulating region has an electrical resistivity that is at least two times greater than an electrical resistivity of the dielectric region.

12. The electrostatic chuck of claim 11 , wherein the insulating region has an electrical resistivity that is at least four times greater than an electrical resistivity of the dielectric region.

13. The electrostatic chuck of claim 12 , wherein the insulating region has an electrical resistivity that is at least eight times greater than an electrical resistivity of the dielectric region.

14. The electrostatic chuck of claim 1 , wherein the dielectric region has an electrical resistivity that is within a range of about 10 8 to about 10 13 ohm-cm.

15. The electrostatic chuck of claim 1 , wherein the insulating region has an electrical resistivity that is within a range of about 10 9 to about 10 14 ohm-cm.

16. A method for processing a semiconductor wafer, comprising:

providing an electrostatic chuck having a chuck body including a dielectric region comprising AlN and an insulating region comprising AlN, an electrode embedded in the chuck body, and a barrier layer provided between dielectric region and the insulating region, wherein the insulating region has a higher electrical resistivity than the dielectric region the dielectric region terminates at a major surface of the electrostatic chuck, defining a chucking surface, and wherein the barrier layer separates the dielectric region from the insulating region to prevent chemical reactions between the dielectric region and the insulating region, or to prevent diffusion of material between the dielectric region and the insulating region;

placing a semiconductor wafer on the chucking surface of the electrostatic chuck;

biasing the electrode, to generate a chucking force to retain the semiconductor wafer on the electrostatic chuck; and

subjecting the semiconductor wafer to a processing operation.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE FIRST ASSIGNOR, AND TO CORRECT THE ASSIGNEES NAME. DOCUMENT PREVIOUSLY RECORDED AT REEL 016376 FRAME 0243. Recorded Aug 16, 2005
From: ZANDI, MORTEZA; VARTABEDIAN, ARA; LACOURSE, BRIAN
To: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
Reel/Frame 016638/0916 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING AND RECEIVING PARTIES, PREVIOUSLY RECORDED AT REEL 016376, FRAME 0243. Recorded Aug 15, 2005
From: ZANDI, MORTEZA; VARTABEDIAN, ARA; LACOURSE, BRIAN
To: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
Reel/Frame 016638/0899 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2005
From: ZANDI, MORTEZ; VARTABEDIAN, ARA; LACOURSE, BRIAN
To: SAINT-GOBAIN CERMAICS & PLASTICS, INC.
Reel/Frame 016376/0243 →
Continuity (2)
Provisional Application 6056237200 · Apr 15, 2004
Related Publication 20050231887A1 · Oct 20, 2005