Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology

1. A trench structure in a semiconductor substrate, comprising:

a silicon oxide filled shallow trench located in a first portion of the semiconductor substrate and having a depth ranging between about 1100 Angstroms and about 2000 Angstroms;

a deep trench located in the insulator filled shallow trench and extending into an underlying second portion of the semiconductor substrate, wherein the deep trench has a depth ranging between about 4 um and about 10 um and a diameter ranging between about 0.5 um and about 1.6 um;

a channel stop region located in a third portion of the semiconductor substrate that is directly underlying the deep trench;

insulator sidewalls located on sides of a bottom portion of the deep trench;

a polysilicon region located in the bottom portion of the deep trench and interfacing the insulator sidewalls; and

a insulator located in a top portion of the deep trench and overlying the polysilicon region, wherein sides of the insulator interface the insulator filled shallow trench, and wherein the insulator comprises silicon oxide.

2. A trench structure in a semiconductor substrate, comprising:

a silicon oxide filled shallow trench located in a first portion of the semiconductor substrate and having a depth ranging between about 1100 Angstroms and about 2000 Angstroms; and

a deep trench located in the insulator filled shallow trench and extending into an underlying second portion of the semiconductor substrate, wherein the deep trench has a depth ranging between about 4 um and about 10 um and a diameter ranging between about 0.5 um and about 1.6 um.

3. The trench structure of claim 2 further comprising a channel stop region located in a third portion of the semiconductor substrate that is directly underlying the deep trench.

4. The trench structure of claim 3 further comprising insulator sidewalls located on sides of a bottom portion of the deep trench.

5. The trench structure of claim 4 further comprising a conductive region located in the bottom portion of the deep trench and interfacing the insulator sidewalls.

6. The trench structure of claim 5 wherein the conductive region is recessed to a depth ranging between about 1000 Angstroms and about 5000 Angstroms below the top surface of the insulator filled shallow trench shape.

7. The trench structure of claim 5 further comprising an insulator layer located in a top portion of the deep trench and overlying the conductive region, wherein sides of the insulator layer interface the insulator filled shallow trench.

8. The trench structure of claim 7 wherein the insulator layer comprises silicon dioxide.

9. The trench structure of claim 7 wherein the insulator layer has a thickness ranging between about 50 Angstroms and about 1000 Angstroms.

10. The trench structure of claim 7 wherein the insulator layer has a smooth top surface topography.

11. The trench structure of claim 2 wherein a region located in a third portion of the semiconductor substrate that is directly underlying the bottom of the deep trench shape is a P type channel stop region.

12. The trench structure of claim 2 further comprising:

a channel stop region located in a third portion of the semiconductor substrate that is directly underlying the deep trench;

insulator sidewalls located on sides of a bottom portion of the deep trench;

a conductive region located in the bottom portion of the deep trench and interfacing the insulator sidewalls, wherein the conductive region is recessed to a depth ranging between about 1000 Angstroms and about 5000 Angstroms below the top surface of the insulator filled shallow trench shape; and

an insulator layer located in a top portion of the deep trench and overlying the conductive region, wherein sides of the insulator layer interface the insulator filled shallow trench, wherein the insulator layer comprises silicon dioxide, wherein the insulator layer has a thickness ranging between about 50 Angstroms and about 1000 Angstroms, and wherein the insulator layer has a smooth top surface topography;

wherein a region located in a third portion of the semiconductor substrate that is directly underlying the bottom of the deep trench shape is a P type channel stop region.