Multi-port processor architecture with bidirectional interfaces between busses
View Patent ↗A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couples the first bus to the second bus. Optionally, the first bus or the second bus can be connected to a memory. The architecture can include a third bus with a third bus to first bus bi-directional interface connecting the third bus to the first bus and a third bus to second bus bi-directional interface connecting the third bus to the second bus. If there are additional bus systems, the Nth port (where N is an integer greater than 2) is connected to the Nth port. The buses use bi-directional interfaces to communicate with each other without using CPU or memory resources, reducing memory access latency.
1. A multi-port processor architecture, comprising:
a first bus;
a second bus;
a central processing unit having a first port coupled to the first bus and a second port coupled to the second bus;
a first bus to second bus bi-directional interface;
a third bus;
a third bus to first bus bi-directional interface connecting the third bus to the first bus; and
a third bus to second bus bi-directional interface connecting the third bus to the second bus.
2. The architecture of claim 1 , further comprising a memory coupled to the first bus.
3. The architecture of claim 2 , further comprising a second central processing unit, the second central processing unit having a first port coupled to the first bus and a second port coupled to the second bus.
4. The architecture of claim 3 wherein at least one of the first bus the second bus and the third bus is a bi-directional bus.
5. The architecture of claim 4 wherein at least one of the first bus to second bus bi-directional interface, the third bus to first bus bi-directional interface, and the third bus to second bus bi-directional interface comprises an open core protocol compliant interface.
6. The architecture of claim 5 , wherein at least one of a group consisting of the first bus, the second bus and the third bus is connected to a memory.
7. The architecture of claim 5 , wherein at least one of a group consisting of the first bus, the second bus and the third bus is a bi-directional bus.
8. The architecture of claim 5 , further comprising a second central processing unit, the second central processing unit having a first port coupled to the first bus and a second port coupled to the second bus.
9. The architecture of claim 5 , further comprising:
a fourth bus;
a fourth bus to first bus bi-directional interface connecting the fourth bus to the first bus;
a fourth bus to second bus bi-directional interface connecting the fourth bus to the second bus; and
a fourth bus to third bus-bi-directional interface connecting the fourth bus to the third bus.
10. The architecture of claim 9 , further comprising:
a fifth bus; and
a fifth bus to second bus bi-directional interface connecting the fifth bus to the second bus.
11. A system on a chip architecture, comprising:
a first bi-directional bus;
a memory connected to the first bus;
a second bi-directional bus;
a central processing unit having a first port coupled to the first bi-directional bus and a second port coupled to the second bi-directional bus;
a first bi-directional bus to second bi-directional bus bi-directional interface; a third bi-directional bus;
a third bi-directional bus, to first bi-directional bus bi-directional interface connecting the third bus to the first bus; and
a third bi-directional bus to second bi-directional bus bi-directional interface connecting the third bus to the second bus.
12. The architecture of claim 11 further comprising:
a fourth bi-directional bus;
a fourth bi-directional bus to first bi-directional bus bi-directional interface connecting the fourth bi-directional bus to the first bi-directional bus;
a fourth bus to second bus bi-directional interface connecting the fourth bi-directional bus to the second bi-directional bus; and
a fourth bi-directional bus to third bi-directional bus-bi-directional interface connecting the fourth bi-directional bus to the third bi-directional bus.
13. The architecture of claim 12 , further comprising:
a bi-directional fifth bus; and
a fifth bi-directional bus to second bus bi-directional interface connecting the fifth bi-directional bus to the second bi-directional bus.
14. The architecture of claim 13 , further comprising a second central processing unit having a first port coupled to the first bus and a second port coupled to the second bus.