Executing background writes to idle DIMMs
View Patent ↗Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
1. In a memory subsystem with a memory controller coupled via a cascaded memory channel to buffered memory modules having write buffers, a method comprising:
receiving a write operation at the memory controller;
immediately forwarding write data of the write operation to a target memory module, wherein the write data is placed in one of a plurality of buffers on the target memory module; and
subsequently issuing a write address to complete the write operation at the target memory module at a later time at which the memory module is not busy.
2. The method of claim 1 , further comprising:
determining when the memory module is not busy by:
tracking a time of completion for each previous operation sent to the target memory module; and
checking whether there are any read operations pending within the memory controller addressed to the target memory module; and
issuing the write address only when each previous operation is completed and when there are no read operations pending within the memory controller.
3. The method of claim 1 , wherein said forwarding of the write data forward the write data on a next available hole in a write data bus.