Semiconductor memory devices including precharge circuit and methods for precharging
A precharge circuit of a semiconductor memory device may include a precharge controller, a first precharge unit and a second precharge unit. The precharge controller may enable a first control signal in a precharge mode for a first operation, and may enable a second control signal in a precharge mode for a second operation. The first precharge unit may precharge a pair of I/O lines to a first voltage in response to the first control signal in the precharge mode for the first operation. The second precharge unit may precharge the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal in the precharge mode for the second operation.
1. A precharge circuit comprising:
a precharge controller configured to enable a first control signal in a precharge mode for a read operation, and enable a second control signal in a precharge mode for a write operation;
a first precharge unit configured to precharge a pair of I/O lines to a first voltage in response to the first control signal in the precharge mode for the read operation; and
a second precharge unit configured to precharge the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal in the precharge mode for the write operation.
2. The precharge circuit of claim 1 , wherein the first precharge unit is coupled between the pair of I/O lines and includes a plurality of transistors serially coupled to each other.
3. The precharge circuit of claim 2 , wherein the plurality of transistors are PMOS transistors.
4. The precharge circuit of claim 1 , wherein the second precharge unit is coupled between the pair of I/O lines and includes a plurality of transistors serially coupled to each other.
5. The precharge circuit of claim 4 , wherein the plurality of transistors are NMOS transistors.
6. The precharge circuit of claim 2 , wherein the first precharge unit includes,
a first PMOS transistor configured to provide the first voltage to a first I/O line of the pair of I/O lines in response to the first control signal; and
a second PMOS transistor configured to provide the first voltage to a second I/O line of the pair of I/O lines in response to the first control signal.
7. The precharge circuit of claim 2 , wherein the second precharge unit includes,
a first NMOS transistor configured to provide the second voltage to a first I/O line of the pair of I/O lines in response to the second control signal; and
a second NMOS transistor configured to provide the second voltage to a second I/O line of the pair of I/O lines in response to the second control signal.
8. The precharge circuit of claim 1 , wherein the first control signal is enabled when a write signal is disabled and a precharge signal is enabled, and the second control signal is enabled when the write signal and the precharge signal are enabled.
9. The precharge circuit of claim 1 , wherein the precharge controller includes,
a first inverter configured to invert a command signal;
a second inverter configured to invert a write signal;
a first NOR gate configured to perform a logical NOR operation on an output signal of the first inverter and an output signal of the second inverter;
a second NOR gate configured to perform a logical NOR operation on the output signal of the first inverter and the write signal;
a first NAND gate configured to perform a logical NAND operation on an output signal of the first NOR gate and the precharge signal;
a third inverter configured to invert an output signal of the first NAND gate, to generate the second control signal; and
a second NAND gate configured to perform a logical NAND operation on an output signal of the second NOR gate and the precharge signal, to generate the first control signal.
10. The precharge circuit of claim 9 , wherein the precharge controller includes a fourth inverter configured to invert a precharge signal, to generate the third control signal.
11. The precharge circuit of claim 1 , further comprising an equalizer configured to equalize the pair of I/O lines in response to a third control signal.
12. The precharge circuit of claim 11 , wherein the equalizer includes a transistor for equalizing the pair of I/O lines in response to the third control signal.
13. The precharge circuit of claim 12 , wherein the transistor included in the equalizer is a PMOS transistor.
14. The precharge circuit of claim 1 , wherein the first control signal is generated when a write signal is disabled and a precharge signal is enabled, and the second control signal is generated when the precharge signal is enabled.
15. The precharge circuit of claim 1 , wherein the precharge controller includes,
a first inverter configured to invert a command signal;
a first NOR gate configured to perform a logical NOR operation on a write signal and an output signal of the first inverter;
a first NAND gate configured to perform a logical NAND operation on the precharge signal and an output signal of the first NOR gate;
a second inverter configured to invert the precharge signal, to generate the third control signal;
a third inverter configured to invert an output signal of the second inverter, to generate the second control signal;
a fourth inverter configured to invert an output signal of the first NAND gate; and
a second NAND gate configured to perform a logical NAND operation on an output signal of the fourth inverter and the second control signal, to generate the first control signal.
16. A semiconductor memory device comprising:
a plurality of pairs of I/O lines;
an I/O line driver configured to drive the pair of I/O lines in response to a write command signal and input data;
a precharge controller configured to enable a first control signal in a precharge mode for a read operation, and enable a second control signal in a precharge mode for a write operation;
a first precharge unit configured to precharge the pair of I/O lines to a first voltage in response to the first control signal in the precharge mode for the read operation; and
a second precharge unit configured to precharge the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal in the precharge mode for the write operation.
17. The semiconductor memory device of claim 16 , further including an equalizer configured to equalize the pair of I/O lines.
18. The semiconductor memory device of claim 16 , wherein the first control signal is enabled when a write signal is disabled and a precharge signal is enabled, and the second control signal is enabled when the write signal and the precharge signal are enabled.
19. The semiconductor memory device of claim 16 , wherein the first control signal is enabled when a write signal is disabled and a precharge signal is enabled, and the second control signal is enabled when the precharge signal is enabled.
20. A method of precharging an input and output (I/O) line of a semiconductor memory device, the method comprising:
generating a first control signal and a second control signal in response to a write signal and a precharge signal;
precharging a pair of I/O lines to a first voltage in response to the first control signal, in a precharge mode for a read operation; and
precharging the pair of I/O lines to a second voltage lower than the first voltage in response to the second control signal, in a precharge mode for a write operation.